Bob Schell

Publication Activity (10 Years)

Years Active: 2007-2020
Publications (10 Years): 2

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Publications

Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya Bhat, Shanthi Pavan
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC (2020)
Bob Schell, Robert Bishop, Jack Kenney
A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor. ESSCIRC (2018)
Bob Schell, Yannis P. Tsividis
Analysis and simulation of continuous-time digital signal processors. Signal Process. 89 (10) (2009)
Bob Schell, Yannis P. Tsividis
A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information. IEEE J. Solid State Circuits 43 (5) (2008)
Bob Schell, Yannis P. Tsividis
A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation. IEEE J. Solid State Circuits 43 (11) (2008)
Bob Schell, Yannis P. Tsividis
A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing. ISSCC (2008)
Bob Schell, Yannis P. Tsividis
Analysis of Continuous-Time Digital Signal Processors. ISCAS (2007)