Prawal Shrestha

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 5

Top Topics

Signal Reconstruction

Digital Holography

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

VLSI Technology and Circuits

IEEE J. Solid State Circuits

Publications

Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury
22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors. ISSCC (2024)
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. IEEE J. Solid State Circuits 59 (4) (2024)
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits (2023)
Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya Bhat, Shanthi Pavan
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC (2020)
Jialin Zhao, Yunzhi Dong, Wenhua Yang, Hajime Shibata, Prawal Shrestha, Zhao Li, Trevor C. Caldwell, José B. Silva, Jeffrey C. Gealow
A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique. IEEE Trans. Circuits Syst. II Express Briefs (7) (2018)