Hae-Seung Lee

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 23

Top Topics

Synthetic Aperture Radar

Reinforcement Learning

Top Venues

IEEE J. Solid State Circuits

Publications

Tanner Andrulis, Ruicong Chen, Hae-Seung Lee, Joel S. Emer, Vivienne Sze
Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design. CoRR (2024)
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. IEEE J. Solid State Circuits 59 (4) (2024)
Jessica Zheng, Hanrui Wang, Anand Chandrasekhar, Aaron D. Aguirre, Song Han, Hae-Seung Lee, Charles G. Sodini
Machine Learning for Arterial Blood Pressure Prediction. CHIL (2023)
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits (2023)
Ruicong Chen, Anantha P. Chandrakasan, Hae-Seung Lee
Sniff-SAR: A 9.8fJ/c.-s 12b secure ADC with detectiondriven protection against power and EM side-channel attack. CICC (2023)
Ruicong Chen, Hanrui Wang, Anantha P. Chandrakasan, Hae-Seung Lee
RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack Resilience. VLSI Technology and Circuits (2022)
Ruicong Chen, H. T. Kung, Anantha P. Chandrakasan, Hae-Seung Lee
A Bit-level Sparsity-aware SAR ADC with Direct Hybrid Encoding for Signed Expressions for AIoT Applications. ISLPED (2022)
Joohyun Seo, Hae-Seung Lee, Charles G. Sodini
Non-Invasive Evaluation of a Carotid Arterial Pressure Waveform Using Motion-Tolerant Ultrasound Measurements During the Valsalva Maneuver. IEEE J. Biomed. Health Informatics 25 (1) (2021)
Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee
S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance. IEEE J. Solid State Circuits 56 (3) (2021)
Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. CoRR (2020)
Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. DAC (2020)
Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee
S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance. CICC (2020)
Xi Yang, Seung-Jun Bae, Hae-Seung Lee
An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS. ESSCIRC (2019)
Xi Yang, Hae-Seung Lee
-order Continuous-time Bandpass Delta-Sigma Modulator with 250 MHz IF, 25 MHz Bandwidth, and over 75 dB SNDR. ISCAS (2018)
Hanrui Wang, Jiacheng Yang, Hae-Seung Lee, Song Han
Learning to Design Circuits. CoRR (2018)
Sirma Orguc, Harneet Singh Khurana, Konstantina M. Stankovic, Hae-Seung Lee, Anantha P. Chandrakasan
EMG-based Real Time Facial Gesture Recognition for Stress Monitoring. EMBC (2018)
Joohyun Seo, Charles G. Sodini, Hae-Seung Lee
Monitoring of Pulse Pressure and Arterial Pressure Waveform Changes during the Valsalva Maneuver by a Portable Ultrasound System. EMBC (2018)
Harneet Singh Khurana, Anantha P. Chandrakasan, Hae-Seung Lee
Recode then LSB-first SAR ADC for Reducing Energy and Bit-cycles. ISCAS (2018)
Sirma Orguc, Harneet Singh Khurana, Hae-Seung Lee, Anantha P. Chandrakasan
0.3 V ultra-low power sensor interface for EMG. ESSCIRC (2017)
Kailiang Chen, Hae-Seung Lee, Charles G. Sodini
A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging. IEEE J. Solid State Circuits 51 (3) (2016)
David Robertson, Aaron Buchwald, Michael Flynn, Hae-Seung Lee, Un-Ku Moon, Boris Murmann
Data converter reflections: 19 papers from the last ten years that deserve a second look. ESSCIRC (2016)
Daniel Prashanth, Hae-Seung Lee
A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs. ACM Great Lakes Symposium on VLSI (2016)
Xi Yang, Hae-Seung Lee
Design of a 4th-order multi-stage feedforward operational amplifier for continuous-time bandpass delta sigma modulators. ISCAS (2016)
SungWon Chung, Hae-Seung Lee
A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT. CICC (2015)
Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee
15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS. ISSCC (2015)
Hyun Ho Boo, Duane S. Boning, Hae-Seung Lee
15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers. ISSCC (2015)
Hyun Ho Boo, Duane S. Boning, Hae-Seung Lee
A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers. IEEE J. Solid State Circuits 50 (12) (2015)
Joohyun Seo, Sabino J. Pietrangelo, Hae-Seung Lee, Charles G. Sodini
Carotid arterial blood pressure waveform monitoring using a portable ultrasound system. EMBC (2015)
Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee
A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS. IEEE J. Solid State Circuits 50 (12) (2015)
Hae-Seung Lee, Seng-Pan Li
Session 26 overview: Nyquist-rate converters: Data converters subcommittee. ISSCC (2015)
Dong-Young Chang, Carlos E. Muñoz, Denis C. Daly, Soon-Kyun Shin, Kevin Guay, Thomas Thurston, Hae-Seung Lee, Kush Gulati, Matthew Z. Straayer
11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. ISSCC (2014)
Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer
A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. IEEE J. Solid State Circuits 49 (6) (2014)
Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration. ISSCC (2014)
Kailiang Chen, Hae-Seung Lee, Charles G. Sodini
A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging. VLSIC (2014)
Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration. IEEE J. Solid State Circuits 49 (12) (2014)
Kailiang Chen, Hae-Seung Lee, Anantha P. Chandrakasan, Charles G. Sodini
Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver. IEEE J. Solid State Circuits 48 (11) (2013)
Albert H. Chang, Hae-Seung Lee, Duane S. Boning
A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration. ESSCIRC (2013)
Do-Yeon Yoon, Hae-Seung Lee, Jeffrey Gealow
Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators. MWSCAS (2013)
Nan Sun, Hae-Seung Lee, Donhee Ham
A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration. ESSCIRC (2012)
Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC. IEEE J. Solid State Circuits 47 (7) (2012)
Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer
A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. CICC (2012)
Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee
A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC. ESSCIRC (2011)
Payam Lajevardi, Anantha P. Chandrakasan, Hae-Seung Lee
Zero-Crossing Detector Based Reconfigurable Analog System. IEEE J. Solid State Circuits 46 (11) (2011)
Albert H. Chang, Hae-Seung Lee, Duane S. Boning
Redundancy in SAR ADCs. ACM Great Lakes Symposium on VLSI (2011)
Albert Chow, Hae-Seung Lee
Offset cancellation for zero crossing based circuits. ISCAS (2010)
Hae-Seung Lee, Lane Brooks, Charles G. Sodini
Zero-Crossing-Based Ultra-Low-Power A/D Converters. Proc. IEEE 98 (2) (2010)
Lane Brooks, Hae-Seung Lee
A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB. ISSCC (2009)
Lane Brooks, Hae-Seung Lee
A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC. IEEE J. Solid State Circuits 44 (12) (2009)
Todd Sepke, Peter Holloway, Charles G. Sodini, Hae-Seung Lee
Noise Analysis for Comparator-Based Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2009)
Lane Brooks, Hae-Seung Lee
Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2008)
Nan Sun, Hae-Seung Lee, Donhee Ham
Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching. IEEE Trans. Circuits Syst. II Express Briefs (9) (2008)
Moo-Yeol Choi, Sung-No Lee, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim, Hae-Seung Lee
A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. CICC (2008)
Hae-Seung Lee, Charles G. Sodini
Analog-to-Digital Converters: Digitizing the Analog World. Proc. IEEE 96 (2) (2008)
Tae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim, Hae-Seung Lee
A 16b 10MS/s digitally self-calibrated ADC with time constant control. CICC (2008)
Lane Brooks, Hae-Seung Lee
A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC. IEEE J. Solid State Circuits 42 (12) (2007)
Lane Brooks, Hae-Seung Lee
A Zero-Crossing-Based 8b 200MS/s Pipelined ADC. ISSCC (2007)
Ho-Young Lee, Tae-Hwan Oh, Ho-Jin Park, Hae-Seung Lee, Mark Spaeth, Jae-Whui Kim
Pipelined ADC with On-Chip Digital Self-Calibration. CICC (2007)
Albert Chow, Hae-Seung Lee
Transient Noise Analysis for Comparator-Based Switched-Capacitor Circuits. ISCAS (2007)
Jungwook Yang, Keith Fife, Lane Brooks, Charles G. Sodini, Andrew Betts, Pavan Mudunuru, Hae-Seung Lee
A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor. ISSCC (2006)
John K. Fiorenza, Todd Sepke, Peter Holloway, Charles G. Sodini, Hae-Seung Lee
Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies. IEEE J. Solid State Circuits 41 (12) (2006)
Todd Sepke, John K. Fiorenza, Charles G. Sodini, Peter Holloway, Hae-Seung Lee
Comparator-based switched-capacitor circuits for scaled CMOS technologies. ISSCC (2006)
Andrew R. Chen, Akintunde Ibitayo (Tayo) Akinwande, Hae-Seung Lee
CMOS-based microdisplay with calibrated backplane. IEEE J. Solid State Circuits 40 (12) (2005)
Susan Luschas, Richard Schreier, Hae-Seung Lee
Radio frequency digital-to-analog converter. IEEE J. Solid State Circuits 39 (9) (2004)
Mark Shane Peng, Hae-Seung Lee
Study of substrate noise and techniques for minimization. IEEE J. Solid State Circuits 39 (11) (2004)
Susan Luschas, Hae-Seung Lee
Output impedance requirements for DACs. ISCAS (1) (2003)
John F. Bulzacchelli, Hae-Seung Lee, James A. Misewich, Mark B. Ketchen
Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate. IEEE J. Solid State Circuits 37 (12) (2002)
Ayman Shabra, Hae-Seung Lee
Oversampled pipeline A/D converters with mismatch shaping. IEEE J. Solid State Circuits 37 (5) (2002)
Kush Gulati, Hae-Seung Lee
A low-power reconfigurable analog-to-digital converter. IEEE J. Solid State Circuits 36 (12) (2001)
Kush Gulati, Hae-Seung Lee
Corrections to "a high-swing CMOS telescopic operational amplifier". IEEE J. Solid State Circuits 35 (1) (2000)
Susanne A. Paul, Hae-Seung Lee, John Goodrich, Titiimaea F. Alailima, Daniel D. Santiago
A Nyquist-rate pipelined oversampling A/D converter. IEEE J. Solid State Circuits 34 (12) (1999)
Kush Gulati, Hae-Seung Lee
A high-swing CMOS telescopic operational amplifier. IEEE J. Solid State Circuits 33 (12) (1998)
David A. Martin, Hae-Seung Lee, Ichiro Masaki
A mixed-signal array processor with early vision applications. IEEE J. Solid State Circuits 33 (3) (1998)
Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung Lee, John L. Wyatt Jr.
Estimating the Focus of Expansion in Analog VLSI. Int. J. Comput. Vis. 28 (3) (1998)
Susanne A. Paul, Hae-Seung Lee
A 9-b charge-to-digital converter for integrated image sensors. IEEE J. Solid State Circuits 31 (12) (1996)
Paul C. Yu, Hae-Seung Lee
A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC. IEEE J. Solid State Circuits 31 (12) (1996)
Hae-Seung Lee
A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC. IEEE J. Solid State Circuits 29 (4) (1994)
S. Nadeem, Charles G. Sodini, Hae-Seung Lee
16-channel oversampled analog-to-digital converter. IEEE J. Solid State Circuits 29 (9) (1994)
Barry Thompson, Hae-Seung Lee, Lawrence M. DeVito
A 300-MHz BiCMOS serial data transceiver. IEEE J. Solid State Circuits 29 (3) (1994)
Theodore L. Tewksbury, Hae-Seung Lee
Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs. IEEE J. Solid State Circuits 29 (3) (1994)
John L. Wyatt Jr., Craig Keast, Mark Seidel, David L. Standley, Berthold K. P. Horn, Tom Knight, Charles G. Sodini, Hae-Seung Lee, Tomaso A. Poggio
Analog VLSI systems for image acquisition and fast early vision processing. Int. J. Comput. Vis. 8 (3) (1992)