Kamlesh Singh

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 14

Top Topics

Power Management

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Shima Sedighiani, Kamlesh Singh, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods. IEEE Trans. Circuits Syst. II Express Briefs 70 (7) (2023)
Shima Sedighiani, Kamlesh Singh, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT. ISQED (2021)
Kamlesh Singh, José Pineda de Gyvez
Twenty Years of Near/Sub-Threshold Design Trends and Enablement. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Shima Sedighiani, Kamlesh Singh, Roel Jordans, Pieter Harpe
Management of Unpredictable Harvested-Energy IoT Devices. ICECS (2021)
Barry de Bruin, Kamlesh Singh, Ying Wang, Jos Huisken, José Pineda de Gyvez, Henk Corporaal
Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection. IEEE Trans. Biomed. Circuits Syst. 15 (5) (2021)
Kamlesh Singh, Barry de Bruin, Hailong Jiao, Jos Huisken, Henk Corporaal, José Pineda de Gyvez
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Shima Sedighiani, Kamlesh Singh, Jos Huisken, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT. MECO (2020)
Jinbo Zhou, Kamlesh Singh, Jos Huisken
Standard Cell based Memory Compiler for Near/Sub-threshold Operation. ICECS (2020)
Barry de Bruin, Kamlesh Singh, Jos Huisken, Henk Corporaal
BrainWave: an energy-efficient EEG monitoring system - evaluation and trade-offs. ISLPED (2020)
Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, José Pineda de Gyvez
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. SoCC (2019)
Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken, José Pineda de Gyvez
Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. ISCAS (2018)
Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
Low power latch based design with smart retiming. ISQED (2018)
Kamlesh Singh
Analysis and Modeling of Chopping Phase Non-Overlap in Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Kamlesh Singh, Shanthi Pavan
A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition. VLSI Design (2016)