Low power latch based design with smart retiming.
Kamlesh SinghHailong JiaoJos HuiskenHamed FatemiJosé Pineda de GyvezPublished in: ISQED (2018)
Keyphrases
- low power
- power consumption
- single chip
- low power consumption
- low cost
- high speed
- vlsi architecture
- logic circuits
- digital signal processing
- power reduction
- gate array
- cmos technology
- power dissipation
- mixed signal
- high power
- ultra low power
- vlsi circuits
- wireless transmission
- nm technology
- real time
- image sensor
- high density