Hamed Fatemi

Publication Activity (10 Years)

Years Active: 2005-2020
Publications (10 Years): 18

Top Topics

Power Reduction

Heuristic Methods

Functional Units

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez
Heuristic Methods for Fine-Grain Exploitation of FDSOI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez
-active dynamic power. SLIP (2020)
Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention. IEEE Trans. Very Large Scale Integr. Syst. 27 (5) (2019)
P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs. Integr. 67 (2019)
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
Enhancing sensitivity-based power reduction for an industry IC design context. Integr. 66 (2019)
Emad A. Ibrahim, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network. DSD (2019)
P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs. PATMOS (2018)
Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
Low power latch based design with smart retiming. ISQED (2018)
Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez
Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths. ACM Great Lakes Symposium on VLSI (2018)
Xun Jiao, Abbas Rahimi, Yu Jiang, Jianguo Wang, Hamed Fatemi, José Pineda de Gyvez, Rajesh K. Gupta
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units. IEEE Trans. Computers 67 (6) (2018)
Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez
Floorplan and placement methodology for improved energy reduction in stacked power-domain design. ASP-DAC (2017)
Pascal Alexander Hager, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
A scan-chain based state retention methodology for IoT processors operating on intermittent energy. DATE (2017)
Andres Gomez, Andrea Bartolini, Davide Rossi, Baris Can Kara, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors. Microprocess. Microsystems 53 (2017)
Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez
Logic Design Partitioning for Stacked Power Domains. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, Kofi A. A. Makinwa, José Pineda de Gyvez
A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling. IEEE J. Solid State Circuits 52 (4) (2017)
Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, José Pineda de Gyvez
Lower power by voltage stacking: a fine-grained system design approach. DAC (2016)
José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt
Circuit valorization in the IC design ecosystem. ICCAD (2016)
Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, José Pineda de Gyvez, Kofi A. A. Makinwa
A microcontroller with 96% power-conversion efficiency using stacked voltage domains. VLSI Circuits (2016)
Xun Jiao, Abbas Rahimi, Balakrishnan Narayanaswamy, Hamed Fatemi, José Pineda de Gyvez, Rajesh K. Gupta
Supervised learning based model for predicting variability-induced timing errors. NEWCAS (2015)
Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, José Pineda de Gyvez
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. DATE (2015)
Ajay Kapoor, Cas Groot, Gerard Villar Pique, Hamed Fatemi, Juan Diego Echeverri, Leo Sevat, Maarten Vertregt, Maurice Meijer, Vibhu Sharma, Yu Pu, José Pineda de Gyvez
Digital Systems Power Management for High Performance Mixed Signal Platforms. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2014)
Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez
Sliding-Mode Control to Compensate PVT Variations in dual core systems. DATE (2012)
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Corporaal
DC-SIMD : Dynamic communication for SIMD processors. IPDPS (2008)
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten
Dynamic-SIMD for lens distortion compensation. ASAP (2006)
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter P. Jonker
Run-time reconfiguration of communication in SIMD architectures. IPDPS (2006)
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard P. Kleihorst
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications. J. Embed. Comput. 2 (2) (2006)
Hamed Fatemi, Henk Corporaal, Twan Basten, Richard P. Kleihorst, Pieter P. Jonker
Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures. ACIVS (2005)