Maarten Vertregt

Publication Activity (10 Years)

Years Active: 1994-2016
Publications (10 Years): 1

Top Topics

Design Patterns

Power Management

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt
Circuit valorization in the IC design ecosystem. ICCAD (2016)
Ajay Kapoor, Cas Groot, Gerard Villar Pique, Hamed Fatemi, Juan Diego Echeverri, Leo Sevat, Maarten Vertregt, Maurice Meijer, Vibhu Sharma, Yu Pu, José Pineda de Gyvez
Digital Systems Power Management for High Performance Mixed Signal Platforms. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2014)
Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez
Standard cell library tuning for variability tolerant designs. DATE (2014)
Fabian van Houwelingen, Ed van Tuijl, Bram Nauta, Maarten Vertregt
A narrow-to-wideband scrambling technique increasing software radio receiver linearity. ESSCIRC (2011)
René Penning de Vries, Hans Rijns, Maarten Vertregt
High performance mixed signal: Business and technology. ESSCIRC (2010)
Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt
A forward body bias generator for digital CMOS circuits with supply voltage scaling. ISCAS (2010)
Hans Van de Vel, Berry A. J. Buter, Hendrik van der Ploeg, Maarten Vertregt, Govert J. G. M. Geelen, Edward J. F. Paulus
A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS. IEEE J. Solid State Circuits 44 (4) (2009)
Paul Veldhorst, George Goksun, Anne-Johan Annema, Bram Nauta, Berry A. J. Buter, Maarten Vertregt
A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. ESSCIRC (2009)
Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, Bram Nauta
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. IEEE J. Solid State Circuits 43 (4) (2008)
Simon M. Louwsma, Ed van Tuijl, Maarten Vertregt, Bram Nauta
A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. CICC (2007)
Hendrik van der Ploeg, Maarten Vertregt, Marco Lammers
A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications. IEEE J. Solid State Circuits 41 (7) (2006)
Hendrik van der Ploeg, Maarten Vertregt, Marco Lammers
A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications. ESSCIRC (2005)
Peter C. S. Scholtens, David Smola, Maarten Vertregt
Systematic power reduction and performance analysis of mismatch limited ADC designs. ISLPED (2005)
Maarten Vertregt, Peter C. S. Scholtens
Assessment of the merits of CMOS technology scaling for analog circuit design. ESSCIRC (2004)
Simon M. Louwsma, E. J. M. van Tuijl, Maarten Vertregt, Peter C. S. Scholtens, Bram Nauta
A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. ESSCIRC (2004)
Amir Zjajo, Hendrik van der Ploeg, Maarten Vertregt
A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μm CMOS. ESSCIRC (2003)
Peter C. S. Scholtens, Maarten Vertregt
A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination. IEEE J. Solid State Circuits 37 (12) (2002)
Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt
A Mixed-Signal Design Roadmap. IEEE Des. Test Comput. 18 (6) (2001)
Hendrik van der Ploeg, Gian Hoogzaad, Henk A. H. Termeer, Maarten Vertregt, Raf L. J. Roovers
with mixed-signal chopping and calibration. IEEE J. Solid State Circuits 36 (12) (2001)
Marcel J. M. Pelgrom, Maarten Vertregt
BiCMOS and CMOS: a long term relation. ICECS (1996)
Marcel J. M. Pelgrom, A. C. Jeannet v. Rens, Maarten Vertregt, Marcel B. Dijkstra
A 25-Ms/s 8-bit CMOS A/D converter for embedded application. IEEE J. Solid State Circuits 29 (8) (1994)