A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS.
Hans Van de VelBerry A. J. ButerHendrik van der PloegMaarten VertregtGovert J. G. M. GeelenEdward J. F. PaulusPublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- power consumption
- nm technology
- cmos technology
- power supply
- hd video
- low power
- analog to digital converter
- silicon on insulator
- single chip
- power management
- high definition
- processing pipeline
- metal oxide semiconductor
- low voltage
- power dissipation
- uncalibrated cameras
- multi view
- multiple sclerosis
- pipeline architecture
- high speed
- low cost
- real time
- analog vlsi
- stereo camera
- image sequences