Piet Wambacq

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 75

Top Venues

IEEE J. Solid State Circuits

ISSCC

ESSCIRC

A-SSCC

Publications

Ali Safa, Wout Mommen, Piet Wambacq, Lars Keuninckx
Resource-Efficient Gesture Recognition Using Low-Resolution Thermal Camera via Spiking Neural Networks and Sparse Segmentation. FG (2024)
Dongyang Yan, Sehoon Park, Yang Zhang, Mark Ingels, Piet Wambacq
A Compact K-band, Asymmetric Coupler-based, Switchless Transmit-Receive Front-End in 0.15μm GaN-on-SiC Technology. ESSCIRC (2023)
Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx
Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout. IEEE J. Solid State Circuits 58 (6) (2023)
Dongyang Yan, Yang Zhang, Dries Peumans, Mark Ingels, Piet Wambacq
A 33 dBm, >30% PAE GaN Power Amplifier Based on a Sub-Quarter-Wavelength Balun for 5G Applications. BCICTS (2023)
Johan Nguyen, Khaled Khalaf, Xinyan Tang, Steven Brebels, Kristof Vaesen, Mithlesh Shrivas, Piet Wambacq
Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS. IEEE J. Solid State Circuits 58 (8) (2023)
Piet Wambacq
Foreword: Building on 70 Years of Innovation in Solid-State Circuit Design. ISSCC (2023)
Dongyang Yan, Yang Zhang, Mark Ingels, Piet Wambacq
A 0.13μm GaAs HEMT Reconfigurable Balance-to-Doherty Stacked Power Amplifier for 5G mm-wave Applications. PRIME (2023)
Devin Verreck, Piet Wambacq, Maarten Van De Put, Zubair Ahmed, Quentin Smets, Aryan Afzalian, Rutger Duflou, Xiangyu Wu, Gioele Mirabelli, Rongmei Chen, Inge Asselberghs, Gouri Sankar Kar
The Promise of 2-D Materials for Scaled Digital and Analog Applications. ISSCC (2023)
Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC (2023)
Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. ISSCC (2023)
Sriram Balamurali, Giovanni Mangraviti, Zhiwei Zhong, Piet Wambacq, Jan Craninckx
A 13-16 GHz Low-Noise Oscillator with Enhanced Tank Energy in 22-nm FDSOI. ESSCIRC (2023)
Rana ElKashlan, Hao Yu, Ahmad Khaled, Sachin Yadav, Uthayasankaran Peralagu, AliReza Alian, Nadine Collaert, Piet Wambacq, Bertrand Parvais
A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs. ESSDERC (2023)
Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits 57 (7) (2022)
Steven Van Winckel, Alican Çaglar, Benjamin Gys, Steven Brebels, Anton Potocnik, Bertrand Parvais, Piet Wambacq, Jan Craninckx
A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout. ESSCIRC (2022)
Xinyan Tang, Johan Nguyen, Giovanni Mangraviti, Zhiwei Zong, Piet Wambacq
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS. IEEE J. Solid State Circuits 57 (5) (2022)
Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx
Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS. IEEE J. Solid State Circuits 57 (7) (2022)
Abhitosh Vais, Sachin Yadav, Yves Mols, Bjorn Vermeersch, Komal Vondkar Kodandarama, Marina Baryshnikova, G. Mannaert, R. Alcotte, Geert Boccardi, Piet Wambacq, Bertrand Parvais, R. Langer, Bernardette Kunert, Nadine Collaert
III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance. ESSDERC (2022)
Anirudh Kankuppe, Sehoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Siddhartha Sinha, Piet Wambacq, Jan Craninckx
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS. IEEE J. Solid State Circuits 57 (7) (2022)
Sehoon Park, Dae-Woong Park, Kristof Vaesen, Anirudh Kankuppe, Siddhartha Sinha, Barend van Liempd, Piet Wambacq, Jan Craninckx
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS. IEEE J. Solid State Circuits 57 (7) (2022)
Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. ISCAS (2021)
Yang Zhang, Giovanni Mangraviti, Johan Nguyen, Zhiwei Zong, Piet Wambacq
26.4 A Reflection-Coefficient Sensor for 28GHz Beamforming Transmitters in 22nm FD-SOI CMOS. ISSCC (2021)
Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx
A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS. ESSCIRC (2021)
Anirudh Kankuppe, Sehoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Piet Wambacq, Jan Craninckx
A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS. ESSCIRC (2021)
Yang Zhang, Giovanni Mangraviti, Johan Nguyen, Zhiwei Zong, Kamil Yavuz Kapusuz, Sam Lemey, Hendrik Rogier, Giuseppe Gramegna, Piet Wambacq
A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS. IEEE J. Solid State Circuits 56 (12) (2021)
Akshay Visweswaran, Kristof Vaesen, Miguel Glassee, Anirudh Kankuppe, Siddhartha Sinha, Claude Desset, Thomas Gielen, André Bourdoux, Piet Wambacq
A 28-nm-CMOS Based 145-GHz FMCW Radar: System, Circuits, and Characterization. IEEE J. Solid State Circuits 56 (7) (2021)
Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC (2021)
Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx
A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout. A-SSCC (2021)
Xinyan Tang, Johan Nguyen, Alaaeldien Medra, Khaled Khalaf, Akshay Visweswaran, Björn Debaillie, Piet Wambacq
Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (5) (2020)
Zhiwei Zong, Giovanni Mangraviti, Piet Wambacq
Noise Corner LC-VCO Design Using Flicker Noise Filtering Technique in 22nm FD-SOI. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (5) (2020)
Claude Desset, Piet Wambacq, Yang Zhang, Mark Ingels, André Bourdoux
A flexible power model for mm-wave and THz high-throughput communication systems. PIMRC (2020)
Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE J. Solid State Circuits 55 (12) (2020)
Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. IEEE J. Solid State Circuits 55 (7) (2020)
Zhiwei Zong, Xinyan Tang, Johan Nguyen, Khaled Khalaf, Giovanni Mangraviti, Yao Liu, Piet Wambacq
A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI. CICC (2020)
Pratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC (2020)
Dae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, Kristof Vaesen, Piet Wambacq, Sang-Gug Lee
A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique. VLSI Circuits (2020)
Toshio Yasue, Fortunato Frazzica, Annachiara Spagnolo, David San Segundo Bello, Maarten De Bock, Piet Wambacq, Jan Craninckx
Order Incremental Sigma-Delta with Refined Digitally Implemented Feed-Forward for 2-stage ADC. IEEE SENSORS (2020)
Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits 54 (3) (2019)
Cheng-Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq
A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter. ESSCIRC (2019)
Johan Nguyen, Xinyan Tang, Khaled Khalaf, Björn Debaillie, Piet Wambacq
Systematic Design of On-Chip Matching Networks for D-band Circuits. NEWCAS (2019)
Xinyan Tang, Alaaeldien Medra, Johan Nguyen, Khaled Khalaf, Björn Debaillie, Piet Wambacq
Design of A D-band Transformer-Based Neutralized Class-AB Power Amplifier in Silicon Technologies. NEWCAS (2019)
Akshay Visweswaran, Bastien Vignon, Xinyan Tang, Steven Brebels, Björn Debaillie, Piet Wambacq
A 112-142GHz Power Amplifier with Regenerative Reactive Feedback achieving 17dBm peak Psat at 13% PAE. ESSCIRC (2019)
Steve Blandino, Giovanni Mangraviti, Claude Desset, André Bourdoux, Piet Wambacq, Sofie Pollin
Multi-User Hybrid MIMO at 60 GHz Using 16-Antenna Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2019)
Dongyang Yan, Mark Ingels, Giovanni Mangraviti, Yao Liu, Bertrand Parvais, Niamh Waldron, Nadine Collaert, Piet Wambacq
Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications. NEWCAS (2019)
Akshay Visweswaran, Kristof Vaesen, Siddhartha Sinha, Ilja Ocket, Miguel Glassee, Claude Desset, André Bourdoux, Piet Wambacq
A 145GHz FMCW-Radar Transceiver in 28nm CMOS. ISSCC (2019)
Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits 54 (2) (2019)
Aritra Banerjee, Kristof Vaesen, Akshay Visweswaran, Khaled Khalaf, Qixian Shi, Steven Brebels, Davide Guermandi, Cheng-Hsueh Tsai, Johan Nguyen, Alaa Medra, Yao Liu, Giovanni Mangraviti, Orges Furxhi, Bert Gyselinckx, André Bourdoux, Jan Craninckx, Piet Wambacq
Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper). CICC (2019)
Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits 54 (4) (2019)
Zhiwei Zong, Giovanni Mangraviti, Piet Wambacq
A 22-29 GHz Voltage-Biased LC-VCO with Suppressed Flicker Noise over Tuning Range in 22nm FD-SOI. NEWCAS (2019)
Giuseppe Gramegna, Hua Wang, Piet Wambacq
Session 26 overview: RF techniques for communication and sensing: RF subcommittee. ISSCC (2018)
Bertrand Parvais, Geert Hellings, Marco Simicic, Pieter Weckx, Jérôme Mitard, Doyoung Jang, V. Deshpande, B. van Liempc, Anabela Veloso, A. Vandooren, Niamh Waldron, Piet Wambacq, Nadine Collaert, Diederik Verkest
Scaling CMOS beyond Si FinFET: an analog/RF perspective. ESSDERC (2018)
Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC (2018)
Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits (2018)
Jiayoon Ru, Jaehyouk Choi, Piet Wambacq
Session 15 overview: RF PLLs: RF subcommittee. ISSCC (2018)
Khaled Khalaf, Kristof Vaesen, Steven Brebels, Giovanni Mangraviti, Michael Libois, Charlotte Soens, Wim Van Thillo, Piet Wambacq
A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS. IEEE J. Solid State Circuits 53 (7) (2018)
Lin-Kun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, Jonathan Borremans
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. Sensors 18 (11) (2018)
Hyunchol Shin, Andrea Bevilacqua, Piet Wambacq
Session 23 overview: LO generation: RF subcommittee. ISSCC (2018)
Kohei Onizuka, Abbas Komijani, Piet Wambacq
Session 2 overview: Power amplifiers. ISSCC (2017)
Oscar Elisio Mattia, Davide Guermandi, Guy Torfs, Piet Wambacq
An up to 36Gbps analog baseband equalizer and demodulator for mm-wave wireless communication in 28nm CMOS. CICC (2017)
Cheng-Hsueh Tsai, Giovanni Mangraviti, Qixian Shi, Khaled Khalaf, André Bourdoux, Piet Wambacq
A 54-64.8 GHz subharmonically injection-locked frequency synthesizer with transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS. ESSCIRC (2017)
Andrea Mazzanti, Xiang Gao, Piet Wambacq
Session 19 overview: Frequency generation. ISSCC (2017)
Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
Khaled Khalaf, Kristof Vaesen, Steven Brebels, Giovanni Mangraviti, Michael Libois, Charlotte Soens, Piet Wambacq
A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS. ESSCIRC (2017)
Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, Ilja Ocket, André Bourdoux, Piet Wambacq, Jan Craninckx, Wim Van Thillo
A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. IEEE J. Solid State Circuits 52 (10) (2017)
Brian P. Ginsburg, Payam Heydari, Piet Wambacq
Session 17 overview: TX and RX building blocks. ISSCC (2017)
Khaled Khalaf, Vojkan Vidojkovic, Kristof Vaesen, Michael Libois, Giovanni Mangraviti, Viki Szortyka, Chunshu Li, Bob Verbruggen, Mark Ingels, André Bourdoux, Charlotte Soens, Wim Van Thillo, John R. Long, Piet Wambacq
Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication. IEEE J. Solid State Circuits 51 (7) (2016)
Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits 51 (12) (2016)
Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits 51 (7) (2016)
Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
A Fractional-n subsampling PLL based on a digital-to-time converter. MIPRO (2016)
Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC (2016)
Giovanni Mangraviti, Khaled Khalaf, Qixian Shi, Kristof Vaesen, Davide Guermandi, Vito Giannini, Steven Brebels, Fortunato Frazzica, André Bourdoux, Charlotte Soens, Wim Van Thillo, Piet Wambacq
13.5 A 4-antenna-path beamforming transceiver for 60GHz multi-Gb/s communication in 28nm CMOS. ISSCC (2016)
Alaa Medra, Davide Guermandi, Kristof Vaesen, Steven Brebels, André Bourdoux, Wim Van Thillo, Piet Wambacq, Vito Giannini
An 80 GHz Low-Noise Amplifier Resilient to the TX Spillover in Phase-Modulated Continuous-Wave Radars. IEEE J. Solid State Circuits 51 (5) (2016)
Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise. ISSCC (2016)
Yanxiang Huang, Chunshu Li, Khaled Khalaf, André Bourdoux, Julien Verschueren, Qixian Shi, Piet Wambacq, Sofie Pollin, Wim Dehaene, Liesbet Van der Perre
A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter. A-SSCC (2016)
Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, André Bourdoux, Piet Wambacq, Wim Van Thillo
A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS. A-SSCC (2016)
Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx
20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. ISSCC (2016)
Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC (2015)
Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. ICICDT (2015)
Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. ISSCC (2015)
Bertrand Parvais, Piet Wambacq, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Ken Sawada, Kazuki Nomoto, Tetsuya Oishi, Hiroaki Ammo
A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS. A-SSCC (2015)
Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq
High-speed analog-to-digital converters in downscaled CMOS. ICICDT (2015)
Viki Szortyka, Kuba Raczkowski, Maarten Kuijk, Piet Wambacq
A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2015)
Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. ESSCIRC (2015)
Piet Wambacq, Stefano Pellerano, Sven Mattisson, Shouhei Kousai, Ali Afsahi, Taizo Yamawaki
F5: Advanced RF CMOS transmitter techniques. ISSCC (2015)
Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean
Modeling FinFET metal gate stack resistance for 14nm node and beyond. ICICDT (2015)
Khaled Khalaf, Vojkan Vidojkovic, John R. Long, Piet Wambacq
A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS. ESSCIRC (2015)
Qixian Shi, Davide Guermandi, Jan Craninckx, Piet Wambacq
Flicker noise upconversion mechanisms in K-band CMOS VCOs. A-SSCC (2015)
Chunshu Li, Min Li, Khaled Khalaf, André Bourdoux, Marian Verhelst, Mark Ingels, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre, Sofie Pollin
Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers. J. Signal Process. Syst. 78 (1) (2015)
Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. ESSCIRC (2015)
Davide Guermandi, Qixian Shi, Alaa Medra, Tomohiro Murata, Wim Van Thillo, André Bourdoux, Piet Wambacq, Vito Giannini
19.7 A 79GHz binary phase-modulated continuous-wave radar transceiver with TX-to-RX spillover cancellation in 28nm CMOS. ISSCC (2015)
Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq
A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS. IEEE J. Solid State Circuits 50 (9) (2015)
Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. IEEE J. Solid State Circuits 50 (12) (2015)
Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". IEEE J. Solid State Circuits 50 (2) (2015)
Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, M. Dusa, Arindam Mallik, Sushil Sakhare, B. Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, P. Leray, T.-T. Liu, Kenichi Miyaguchi, Bertrand Parvais, P. Schuddinck, P. Weemaes, Abdelkarim Mercha, Jürgen Bömmels, N. Horiguchi, G. McIntyre, Aaron Thean, Zsolt Tokei, S. Cheng, Diederik Verkest, A. Steegen
Design Technology co-optimization for N10. CICC (2014)
Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. ESSCIRC (2014)
Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq
21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS. ISSCC (2014)
Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq
A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. ESSCIRC (2014)
Alaa Medra, Vito Giannini, Davide Guermandi, Piet Wambacq
A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C. ESSCIRC (2014)
Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC (2014)
Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. IEEE J. Solid State Circuits 49 (5) (2014)
Vito Giannini, Davide Guermandi, Qixian Shi, Kristof Vaesen, Bertrand Parvais, Wim Van Thillo, André Bourdoux, Charlotte Soens, Jan Craninckx, Piet Wambacq
14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. ISSCC (2014)

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Piet Wambacq