Ivan Ciofi

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 14

Top Topics

Drift Detection

Application Level

Reliability Assessment

Top Venues

Microelectron. Reliab.

VLSI Technology and Circuits

Publications

D. Tiernc, Antonio Arreghini, Alicja Lesniewska, Y. Jeong, Marleen H. van der Veen, J. Stiers, N. Bazzazian, Ivan Ciofi, Geert Van den Bosch, Maarten Rosmeulen
Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND. IRPS (2024)
O. Varela Pedreira, Youqi Ding, D. Coenen, Philippe Roussel, A. S. Saleh, Veerle Simons, Houman Zahedmanesh, Ivan Ciofi, Kris Croes
De-Coupling Thermo-Migration from Electromigration Using a Dedicated Test Structure. IRPS (2024)
Y. Fang, Alicja Lesniewska, Ivan Ciofi, Philippe Roussel, Chen Wu, Victor Vega-Gonzalez, Ingrid De Wolf, Kris Croes
BEOL tip-to-tip dielectric reliability characterization using a design-representative test structure. IRPS (2024)
Melina Lofrano, Herman Oprins, Xinyue Chang, Bjorn Vermeersch, Olalla Varela Pedreira, Alicja Lesniewska, Vladimir Cherman, Ivan Ciofi, Kristof Croes, Seongho Park, Zsolt Tokei
Towards accurate temperature prediction in BEOL for reliability assessment (Invited). IRPS (2023)
Houman Zahedmanesh, Philippe Roussel, Ivan Ciofi, Kristof Croes
A pragmatic network-aware paradigm for system-level electromigration predictions at scale. IRPS (2023)
Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Y. Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits (2023)
Olalla Varela Pedreira, Houman Zahedmanesh, Youqi Ding, Ivan Ciofi, Kristof Croes
Challenges for Interconnect Reliability: From Element to System Level. ISPD (2023)
O. Varela Pedreira, Melina Lofrano, Houman Zahedmanesh, Philippe J. Roussel, Marleen H. van der Veen, Veerle Simons, E. Chery, Ivan Ciofi, Kris Croes
Assessment of critical Co electromigration parameters. IRPS (2022)
Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Kristof Croes, Mustafa Badaroglu
System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents. IRPS (2022)
Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes
A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network. SLIP (2021)
Deniz Kocaay, Philippe Roussel, Kristof Croes, Ivan Ciofi, Alicja Lesniewska, Ingrid De Wolf
Method to assess the impact of LER and spacing variation on BEOL dielectric reliability using 2D-field simulations for <20nm spacing. IRPS (2018)
Chen Wu, O. Varela Pedreira, Alicja Lesniewska, Yunlong Li, Ivan Ciofi, Zsolt Tokei, Kris Croes
Insights into metal drift induced failure in MOL and BEOL. IRPS (2018)
Deniz Kocaay, Philippe Roussel, Kris Croes, Ivan Ciofi, Y. Saad, Ingrid De Wolf
LER and spacing variability on BEOL TDDB using E-field mapping: Impact of field acceleration. Microelectron. Reliab. (2017)
Houman Zahedmanesh, Mario Gonzalez, Ivan Ciofi, Kristof Croes, Jürgen Bömmels, Zsolt Tokei
Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation. Microelectron. Reliab. 59 (2016)
Kris Croes, Alicja Lesniewska, Chen Wu, Ivan Ciofi, Agnieszka Banczerowska, B. Briggs, S. Demuynck, Zsolt Tokei, Jürgen Bömmels, Y. Saad, W. Gao
Intrinsic reliability of local interconnects for N7 and beyond. IRPS (2015)
Kris Croes, Deniz Kocaay, Ivan Ciofi, Jürgen Bömmels, Zsolt Tokei
Impact of process variability on BEOL TDDB lifetime model assessment. IRPS (2015)
Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC (2014)
Christoph Kerner, Ivan Ciofi, Thomas Chiarella, Stefaan Van Huylenbroeck
Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques. ESSDERC (2012)
Carmine Ciofi, Ivan Ciofi, Stefano C. Di Pascoli, Bruno Neri
Temperature controlled oven for low noise measurement systems [for electromigration characterization]. IEEE Trans. Instrum. Meas. 49 (3) (2000)