Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Trong Huynh BaoDmitry YakimetsJulien RyckaertIvan CiofiRogier BaertAnabela VelosoJürgen BömmelsNadine CollaertPhilippe RousselS. DemuynckPraveen RaghavanAbdelkarim MerchaZsolt TokeiDiederik VerkestAaron TheanPiet WambacqPublished in: ESSDERC (2014)
Keyphrases
- cmos technology
- nm technology
- metal oxide semiconductor
- low power
- silicon on insulator
- power consumption
- power dissipation
- low cost
- low voltage
- circuit design
- parallel processing
- information society
- computing technologies
- workflow technology
- intellectual property rights
- technical issues
- image sensor
- data mining technology
- rapid development
- enabling technologies
- high speed
- data mining