Dmitry Yakimets

Publication Activity (10 Years)

Years Active: 2013-2017
Publications (10 Years): 2

Top Topics

Metal Oxide Semiconductor

Electronic Devices

Intellectual Property Rights

Top Venues

Publications

Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. ESSDERC (2017)
Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi
Device/system performance modeling of stacked lateral NWFET logic. ISQED (2016)
Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. ICICDT (2015)
Marie Garcia Bardon, P. Schuddinck, Praveen Raghavan, Doyoung Jang, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Thean
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. ICICDT (2015)
Dmitry Yakimets, Doyoung Jang, Praveen Raghavan, Geert Eneman, Hans Mertens, P. Schuddinck, Arindam Mallik, Marie Garcia Bardon, Nadine Collaert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Kristin De Meyer
Lateral NWFET optimization for beyond 7nm nodes. ICICDT (2015)
Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, Anda Mocuta, Dan Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, A. Steegen
Holisitic device exploration for 7nm node. CICC (2015)
Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC (2014)
Doyoung Jang, Marie Garcia Bardon, Dmitry Yakimets, Kenichi Miyaguchi, An De Keersgieter, Thomas Chiarella, Romain Ritzenthaler, Morin Dehan, Abdelkarim Mercha
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. ESSDERC (2013)