Azad Naeemi

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 22

Top Topics

Scientific Inquiry

Advanced Technology

Top Venues

Publications

Siri Narla, Piyush Kumar, Mohammad Adnaan, Azad Naeemi
Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search. CoRR (2024)
Liuting Shang, Azad Naeemi, Chenyun Pan
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis. IEEE Open J. Comput. Soc. 4 (2023)
Yandong Luo, Piyush Kumar, Yu-Ching Liao, William Hwang, Fen Xue, Wilman Tsai, Shan X. Wang, Azad Naeemi, Shimeng Yu
Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators. IMW (2022)
Hai Li, Dmitri E. Nikonov, Chia-Ching Lin, Kerem Camsari, Yu-Ching Liao, Chia-Sheng Hsu, Azad Naeemi, Ian A. Young
Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits. CoRR (2021)
Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). DATE (2020)
Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu
A Mixed Signal Architecture for Convolutional Neural Networks. ACM J. Emerg. Technol. Comput. Syst. 15 (2) (2019)
Aditya Anupam, Shubhangi Gupta, Azad Naeemi, Nassim Parvin
Beyond Motivation and Memorization: Fostering Scientific Inquiry with Games. CHI PLAY (Companion) (2019)
William Scott, Jonathan Jeffrey, Blake Heard, Dmitri E. Nikonov, Ian A. Young, Sasikanth Manipatruni, Azad Naeemi, Rouhollah Mousavi Iraei
Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning. ACM Southeast Regional Conference (2018)
Victor Huang, Chenyun Pan, Azad Naeemi
Generic system-level modeling and optimization for beyond CMOS device applications. ISQED (2018)
Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. DAC (2018)
Aditya Anupam, Ridhima Gupta, Azad Naeemi, Nassim Jafarinaimi
Particle in a Box: An Experiential Environment for Learning Introductory Quantum Mechanics. IEEE Trans. Educ. 61 (1) (2018)
Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu
A mixed signal architecture for convolutional neural networks. CoRR (2018)
Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC (2017)
Chenyun Pan, Azad Naeemi
Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. DATE (2017)
Chenyun Pan, Azad Naeemi
Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications. CoRR (2017)
Rouhollah Mousavi Iraei, Nickvash Kani, Sourav Dutta, Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A. Young, John T. Heron, Azad Naeemi
Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation. CoRR (2017)
Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu
Non-volatile spin wave majority gate at the nanoscale. CoRR (2016)
Sou-Chi Chang, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Azad Naeemi
Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls. CoRR (2016)
Divya Prasad, Chenyun Pan, Azad Naeemi
Impact of interconnect variability on circuit performance in advanced technology nodes. ISQED (2016)
Chenyun Pan, Azad Naeemi
A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices. CoRR (2016)
Javaneh Mohseni, Chenyun Pan, Azad Naeemi
Performance modeling and optimization for on-chip interconnects in 3D memory arrays. ISQED (2016)
Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi
Device/system performance modeling of stacked lateral NWFET logic. ISQED (2016)
Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. ISQED (2015)
Hamidreza Aghasi, Ruohollah Mousavi Iraei, Azad Naeemi, Ehsan Afshari
Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition. CoRR (2015)
Chenyun Pan, Azad Naeemi
A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (1) (2015)
Rose Peng, Bill Dorn, Azad Naeemi, Nassim Jafarinaimi
Interactive visualizations for teaching quantum mechanics and semiconductor physics. FIE (2014)
Sou-Chi Chang, Ahmet Ceyhan, Vachan Kumar, Azad Naeemi
Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits. ISLPED (2014)
Nickvash Kani, Azad Naeemi
Wiring resource minimization for physically-complex Network-on-Chip architectures. SoCC (2014)
Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi
An analytical approach to system-level variation analysis and optimization for multi-core processor. ISQED (2014)
Azad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah M. Iraei, Shaloo Rakheja
BEOL Scaling Limits and Next Generation Technology Prospects. DAC (2014)
Nickvash Kani, Azad Naeemi
Pipeline design in spintronic circuits. NANOARCH (2014)
Shaloo Rakheja, Vachan Kumar, Azad Naeemi
Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects. Proc. IEEE 101 (7) (2013)
Chenyun Pan, Ahmet Ceyhan, Azad Naeemi
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs. ISQED (2013)
Shaloo Rakheja, Vachan Kumar, Azad Naeemi
Performance modeling for interconnects for conventional and emerging switches. SLIP (2013)
Ahmet Ceyhan, Azad Naeemi
Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices. ISQED (2013)
Chenyun Pan, Azad Naeemi
Device- and system-level performance modeling for graphene P-N junction logic. ISQED (2012)
Chenyun Pan, Azad Naeemi
System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model. ICICDT (2012)
Ahmet Ceyhan, Azad Naeemi
System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors. ICICDT (2012)
Shaloo Rakheja, Azad Naeemi
Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits. ISQED (2012)
Aritra Banerjee, Subho Chatterjee, Azad Naeemi, Abhijit Chatterjee
Power Aware Post-manufacture Tuning of Analog Nanocircuits. ETS (2011)
Shaloo Rakheja, Azad Naeemi
Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling. ISQED (2011)
James D. Meindl, Azad Naeemi, Muhannad S. Bakir, R. Murali
Nanoelectronics in retrospect, prospect and principle. ISSCC (2010)
Azad Naeemi, James D. Meindl
Physical models for electron transport in graphene nanoribbons and their junctions. ICCAD (2008)
Muhannad S. Bakir, Calvin King, Deepak C. Sekar, Hiren D. Thacker, Bing Dang, Gang Huang, Azad Naeemi, James D. Meindl
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. CICC (2008)
Azad Naeemi, Reza Sarvari, James D. Meindl
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. DAC (2007)
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl
IntSim: A CAD tool for optimization of multilevel interconnect networks. ICCAD (2007)
Gang Huang, Deepak C. Sekar, Azad Naeemi, Kaveh Shakeri, James D. Meindl
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. CICC (2007)
Azad Naeemi, James D. Meindl
Carbon nanotube interconnects. ISPD (2007)
Azad Naeemi, Muhannad S. Bakir
Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities. SoCC (2006)