Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
Chenyun PanPraveen RaghavanFrancky CatthoorZsolt TokeiAzad NaeemiPublished in: ISQED (2015)
Keyphrases
- nm technology
- power dissipation
- power consumption
- low power
- cmos technology
- optimization algorithm
- logic circuits
- finite state machines
- design methodology
- digital signal processing
- high speed
- optimization problems
- data processing
- analog circuits
- input output
- tree structure
- energy consumption
- optimization method
- case study
- graph structure