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Chenyun Pan
ORCID
Publication Activity (10 Years)
Years Active: 2012-2024
Publications (10 Years): 19
Top Topics
Neural Network
Boolean Logic
Advanced Technology
Future Directions
Top Venues
ISQED
CoRR
MWSCAS
IET Commun.
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Publications
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Sheng Lu
,
Liuting Shang
,
Sungyong Jung
,
Chenyun Pan
Emerging Reconfigurable Logic Device Based FPGA Design and Optimization.
ISQED
(2024)
Chengchen Mao
,
Qilian Liang
,
Chenyun Pan
,
Ioannis D. Schizas
A statistical approach for neural network pruning with application to internet of things.
EURASIP J. Wirel. Commun. Netw.
2023 (1) (2023)
Venkata K. V. V. Bathalapalli
,
Saraju P. Mohanty
,
Chenyun Pan
,
Elias Kougianos
QPUF: Quantum Physical Unclonable Functions for Security-by-Design of Industrial Internet-of-Things.
iSES
(2023)
Liuting Shang
,
Azad Naeemi
,
Chenyun Pan
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis.
IEEE Open J. Comput. Soc.
4 (2023)
Zhenlin Pei
,
Mahta Mayahinia
,
Hsiao-Hsuan Liu
,
Mehdi B. Tahoori
,
Francky Catthoor
,
Zsolt Tokei
,
Chenyun Pan
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.
ACM Great Lakes Symposium on VLSI
(2023)
Zhenlin Pei
,
Mahta Mayahinia
,
Hsiao-Hsuan Liu
,
Mehdi B. Tahoori
,
Shairfe Muhammad Salahuddin
,
Francky Catthoor
,
Zsolt Tokei
,
Chenyun Pan
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.
ISQED
(2023)
Chengchen Mao
,
Zongwen Mu
,
Qilian Liang
,
Ioannis D. Schizas
,
Chenyun Pan
Deep learning in physical layer communications: Evolution and prospects in 5G and 6G networks.
IET Commun.
17 (16) (2023)
Liuting Shang
,
Sheng Lu
,
Sungyong Jung
,
Chenyun Pan
Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis.
MWSCAS
(2023)
Sheng Lu
,
Zhenlin Pei
,
Liuting Shang
,
Sungyong Jung
,
Chenyun Pan
A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices.
MWSCAS
(2023)
Liuting Shang
,
Muhammad Adil
,
Ramtin Madani
,
Chenyun Pan
Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator.
ISVLSI
(2020)
Qiuwen Lou
,
Chenyun Pan
,
John McGuinness
,
András Horváth
,
Azad Naeemi
,
Michael T. Niemier
,
Xiaobo Sharon Hu
A Mixed Signal Architecture for Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst.
15 (2) (2019)
Victor Huang
,
Chenyun Pan
,
Azad Naeemi
Generic system-level modeling and optimization for beyond CMOS device applications.
ISQED
(2018)
Qiuwen Lou
,
Chenyun Pan
,
John McGuinness
,
András Horváth
,
Azad Naeemi
,
Michael T. Niemier
,
Xiaobo Sharon Hu
A mixed signal architecture for convolutional neural networks.
CoRR
(2018)
Chenyun Pan
,
Azad Naeemi
Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions.
DATE
(2017)
Chenyun Pan
,
Azad Naeemi
Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications.
CoRR
(2017)
Divya Prasad
,
Chenyun Pan
,
Azad Naeemi
Impact of interconnect variability on circuit performance in advanced technology nodes.
ISQED
(2016)
Chenyun Pan
,
Azad Naeemi
A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices.
CoRR
(2016)
Javaneh Mohseni
,
Chenyun Pan
,
Azad Naeemi
Performance modeling and optimization for on-chip interconnects in 3D memory arrays.
ISQED
(2016)
Victor Huang
,
Chenyun Pan
,
Dmitry Yakimets
,
Praveen Raghavan
,
Azad Naeemi
Device/system performance modeling of stacked lateral NWFET logic.
ISQED
(2016)
Chenyun Pan
,
Praveen Raghavan
,
Francky Catthoor
,
Zsolt Tokei
,
Azad Naeemi
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
ISQED
(2015)
Chenyun Pan
,
Azad Naeemi
A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies.
IEEE J. Emerg. Sel. Topics Circuits Syst.
5 (1) (2015)
Chenyun Pan
,
Saibal Mukhopadhyay
,
Azad Naeemi
An analytical approach to system-level variation analysis and optimization for multi-core processor.
ISQED
(2014)
Azad Naeemi
,
Ahmet Ceyhan
,
Vachan Kumar
,
Chenyun Pan
,
Rouhollah M. Iraei
,
Shaloo Rakheja
BEOL Scaling Limits and Next Generation Technology Prospects.
DAC
(2014)
Chenyun Pan
,
Ahmet Ceyhan
,
Azad Naeemi
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs.
ISQED
(2013)
Chenyun Pan
,
Azad Naeemi
Device- and system-level performance modeling for graphene P-N junction logic.
ISQED
(2012)
Chenyun Pan
,
Azad Naeemi
System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model.
ICICDT
(2012)