Brian Cline

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 26

Top Topics

Eliminate Redundant

Physical Design

Electron Beam Lithography

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Supreet Jeloka, Brian Cline, Shidhartha Das, Benoit Labbe, Alejandro Rico, Rainer Herberholz, Javier A. DeLaCruz, Rahul Mathur, Shawn Hung
System technology co-optimization and design challenges for 3D IC. CICC (2022)
Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. CoRR (2021)
Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. CICC (2021)
Rakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline
A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance. CICC (2021)
Lingjun Zhu, Lennart Bamberg, Sai Surya Kiran Pentapati, Kyungwook Chang, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Brian Cline, Saurabh Sinha, Xiaoqing Xu, Alberto García-Ortiz, Sung Kyu Lim
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim
Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. ISLPED (2021)
Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR (2020)
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline
-A Microprocessor. ISLPED (2019)
Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. DAC (2018)
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. CoRR (2018)
Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. IEEE Trans. Very Large Scale Integr. Syst. 25 (7) (2017)
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). ICCAD (2017)
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED (2017)
Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan
Redundant Local-Loop Insertion for Unidirectional Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. ICCD (2017)
Nathaniel Ross Pinckney, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw, Lucian Shifren, Brian Cline, Saurabh Sinha
Impact of FinFET on Near-Threshold Voltage Scalability. IEEE Des. Test 34 (2) (2017)
Brian Cline, Saibal Mukhopadhyay, Peter J. Wright, Hai Li, Vinod Viswanath, Paul Wesling, Gang Qu, Ali Iranmanesh
Welcome. ISQED (2016)
Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. IET Comput. Digit. Tech. 10 (6) (2016)
Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. ISLPED (2016)
Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. ICCAD (2016)
Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. DAC (2016)
Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric
ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. 53 (2016)
Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Match-making for monolithic 3D IC: finding the right technology node. DAC (2016)
Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Monolithic 3D IC design: Power, performance, and area impact at 7nm. ISQED (2016)
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov
Circuit design perspectives for Ge FinFET at 10nm and beyond. ISQED (2015)
Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Power benefit study of monolithic 3D IC at the 7nm technology node. ISLPED (2015)
Robert C. Aitken, David Pietromonaco, Brian Cline
DFM is dead - Long live DFM. ICCD (2014)
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
Self-aligned double patterning aware pin access and standard cell layout co-optimization. ISPD (2014)
Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra
Physical design and FinFETs. ISPD (2014)
Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken
The past present and future of design-technology co-optimization. CICC (2013)
Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao
Exploring sub-20nm FinFET design with predictive technology models. DAC (2012)
Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao
Design benchmarking to 7nm with FinFET predictive technology models. ISLPED (2012)
Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal
Mechanical Stress Aware Optimization for Leakage Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw
STEEL: a technique for stress-enhanced standard cell library design. ICCAD (2008)
Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal
Stress aware layout optimization. ISPD (2008)
Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal
Leakage power reduction using stress-enhanced layouts. DAC (2008)
Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran
Transistor-Specific Delay Modeling for SSTA. DATE (2008)
Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd M. Austin, Dennis Sylvester, David T. Blaauw
Exploring Variability and Performance in a Sub-200-mV Processor. IEEE J. Solid State Circuits 43 (4) (2008)
Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao
Analysis and modeling of CD variation for statistical static timing. ICCAD (2006)