Greg Yeric

Publication Activity (10 Years)

Years Active: 2005-2022
Publications (10 Years): 18

Top Topics

Physical Design

Electron Beam Lithography

Top Venues

Publications

Saurabh V. Suryavanshi, Greg Yeric, Max Irby, X. M. Henry Huang, Glen Rosendale, Lucian Shifren
Extreme Temperature (> 200 °C), Radiation Hard (> 1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology. IMW (2022)
Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. CoRR (2021)
Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR (2020)
Greg Yeric
IC Design After Moore's Law. CICC (2019)
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. CoRR (2018)
Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. IEEE Trans. Very Large Scale Integr. Syst. 25 (7) (2017)
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). ICCAD (2017)
Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED (2017)
Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. ICCD (2017)
Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. IET Comput. Digit. Tech. 10 (6) (2016)
Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. ISLPED (2016)
Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. ICCAD (2016)
Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric
ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. 53 (2016)
Greg Yeric
At the core of system scaling. ESSCIRC (2016)
Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Match-making for monolithic 3D IC: finding the right technology node. DAC (2016)
Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Monolithic 3D IC design: Power, performance, and area impact at 7nm. ISQED (2016)
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov
Circuit design perspectives for Ge FinFET at 10nm and beyond. ISQED (2015)
Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Power benefit study of monolithic 3D IC at the 7nm technology node. ISLPED (2015)
Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
Self-aligned double patterning aware pin access and standard cell layout co-optimization. ISPD (2014)
Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra
Physical design and FinFETs. ISPD (2014)
Greg Yeric
Design, technology and yield in the post-moore era. ITC (2014)
Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken
The past present and future of design-technology co-optimization. CICC (2013)
Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao
Exploring sub-20nm FinFET design with predictive technology models. DAC (2012)
Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao
Design benchmarking to 7nm with FinFET predictive technology models. ISLPED (2012)
Rob Aitken, Greg Yeric, David Flynn
Correlating models and silicon for improved parametric yield. DATE (2011)
Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian
Making Manufacturing Work For You. DAC (2007)
Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green
Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below. IEEE Des. Test Comput. 22 (3) (2005)