H.-S. Philip Wong

ORCID

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 55

Top Venues

CoRR

VLSI Technology and Circuits

DRC

DAC

Publications

Keming Fan, Wei-Chen Chen, Sumukh Pinge, H.-S. Philip Wong, Tajana Rosing
Efficient Open Modification Spectral Library Searching in High-Dimensional Space with Multi-Level-Cell Memory. CoRR (2024)
Xiangjin Wu, Asir Intisar Khan, H.-S. Philip Wong, Eric Pop
Optimizing TiTe2/Ge4Sb6Te7 Superlattices Towards Low-Power, Fast-Speed, and High-Stability Phase Change Memory. DRC (2024)
Gert Cauwenberghs, Jason Cong, X. Sharon Hu, Siddharth Joshi, Subhasish Mitra, Wolfgang Porod, H.-S. Philip Wong
Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. Proc. IEEE 111 (6) (2023)
Berivan Isik, Kristy Choi, Xin Zheng, Tsachy Weissman, Stefano Ermon, H.-S. Philip Wong, Armin Alaghi
Neural Network Compression for Noisy Storage Devices. ACM Trans. Embed. Comput. Syst. 22 (3) (2023)
Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen-Feng Hsu, Sheng-Kai Su, Ang-Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying-Mei Yang, Kuang-I Lin, Yun-Yang Shen, Wen-Hao Chang, San Lin Liew, Vincent D.-H. Hou, Jin Cai, Chung-Cheng Wu, Jeff Wu, H.-S. Philip Wong, Xinran Wang, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu
Scaled contact length with low contact resistance in monolayer 2D channel transistors. VLSI Technology and Circuits (2023)
F. Huang, B. Saini, L. Wan, H. Lu, X. He, S. Qin, W. Tsai, A. Gruverman, Andrew C. Meng, H.-S. Philip Wong, P. C. McIntyre, S. S. Wong
First Observation of Ultra-high Polarization (~ 108 μC/cm²) in Nanometer Scaled High Performance Ferroelectric HZO Capacitors with Mo Electrodes. VLSI Technology and Circuits (2023)
Kerem Akarvardar, H.-S. Philip Wong
Technology Prospects for Data-Intensive Computing. Proc. IEEE 111 (1) (2023)
Kasidit Toprasertpong, Shuhan Liu, Jian Chen, Sumaiya Wahid, Koustav Jana, Wei-Chen Chen, Shengman Li, Eric Pop, H.-S. Philip Wong
Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V. VLSI Technology and Circuits (2023)
Gregory Pitner, Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Sheng-Kai Su, Gilad Zeevi, Qing Lin, Hsin-Yuan Chiu, Matthias Passlack, Zichen Zhang, D. Mahaveer Sathaiya, Aslan Wei, Carlo Gilardi, Edward Chen, San Lin Liew, Vincent D.-H. Hou, Chung-Wei Wu, Jeff Wu, Zhiwei Lin, Jeffrey Fagan, Ming Zheng, Han Wang, Subhasish Mitra, H.-S. Philip Wong, Iuliana P. Radu
Building high performance transistors on carbon nanotube channel. VLSI Technology and Circuits (2023)
W.-C. Chen, F. Huang, S. Qin, Z. Yu, Q. Lin, P. C. McIntyre, S. S. Wong, H.-S. Philip Wong
4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in Memory. VLSI Technology and Circuits (2022)
Lauren Hoang, Alwin Daus, Sumaiya Wahid, Jimin Kwon, Jung-Soo Ko, Shengjun Qin, Mahnaz Islam, Krishna C. Saraswat, H.-S. Philip Wong, Eric Pop
Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties. DRC (2022)
Asir Intisar Khan, Christopher Perez, Xiangjin Wu, Byoungjun Won, Kangsik Kim, Heungdong Kwon, Pranav Ramesh, Kathryn M. Neilson, Mehdi Asheghi, Krishna Saraswat, Zonghoon Lee, Il-Kwon Oh, H.-S. Philip Wong, Kenneth E. Goodson, Eric Pop
) and Low Resistance Drift (~0.002 at 105°C). VLSI Technology and Circuits (2022)
Ming-Yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Yuxuan Cosmi Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lin-Yun Huang, Chao-Ching Cheng, Wei-Yen Woon, Szuya Liao, Chih-I Wu, Lain-Jong Li, Iuliana Radu, H.-S. Philip Wong, Han Wang
Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor. VLSI Technology and Circuits (2022)
Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs
A compute-in-memory chip based on resistive random-access memory. Nat. 608 (7923) (2022)
Xin Zheng, Ryan Zarcone, Akash Levy, Win-San Khwa, Priyanka Raina, Bruno A. Olshausen, H.-S. Philip Wong
High-density analog image storage in an analog-valued non-volatile memory array. Neuromorph. Comput. Eng. 2 (4) (2022)
Richard A. Gottscho, Edlyn V. Levine, Tsu-Jae King Liu, Paul C. McIntyre, Subhasish Mitra, Boris Murmann, Jan M. Rabaey, Sayeef S. Salahuddin, Willy C. Shih, H.-S. Philip Wong
Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies. CoRR (2022)
Sumaiya Wahid, Alwin Daus, Jimin Kwon, Shengjun Qin, Jung-Soo Ko, Krishna C. Saraswat, H.-S. Philip Wong, Eric Pop
First Demonstration of Top-Gated ITO Transistors: Effect of Channel Passivation. DRC (2022)
Shengjun Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Simon Wong, H.-S. Philip Wong
8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory. VLSI Technology and Circuits (2022)
Sheng-Kai Su, Edward Chen, Terry Y. T. Hung, Meng-Zhan Li, Gregory Pitner, Chao-Ching Cheng, Han Wang, Jin Cai, H.-S. Philip Wong, Iuliana P. Radu
Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS. VLSI Technology and Circuits (2022)
Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs
Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. CoRR (2021)
Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. CoRR (2021)
Berivan Isik, Kristy Choi, Xin Zheng, Tsachy Weissman, Stefano Ermon, H.-S. Philip Wong, Armin Alaghi
Neural Network Compression for Noisy Storage Devices. CoRR (2021)
Rajkumar Kubendran, Weier Wan, Siddharth Joshi, H.-S. Philip Wong, Gert Cauwenberghs
A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver. ICONS (2020)
Randy Bryant, Mark D. Hill, Tom Kazior, Daniel Lee, Jie Liu, Klara Nahrstedt, Vijay Narayanan, Jan M. Rabaey, Hava T. Siegelmann, Naresh R. Shanbhag, Naveen Verma, H.-S. Philip Wong
Nanotechnology-inspired Information Processing Systems of the Future. CoRR (2020)
H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin
A Density Metric for Semiconductor Technology [Point of View]. Proc. IEEE 108 (4) (2020)
Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. ISSCC (2020)
H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri
Scanning the Issue. Proc. IEEE 108 (4) (2020)
Mindy D. Bishop, H.-S. Philip Wong, Subhasish Mitra, Max M. Shulaker
Monolithic 3-D Integration. IEEE Micro 39 (6) (2019)
Tony F. Wu, Binh Q. Le, Robert Radway, Andrew Bartolo, William Hwang, Seungbin Jeong, Haitong Li, Pulkit Tandon, Elisa Vianello, Pascal Vivet, Etienne Nowak, Mary Wootters, H.-S. Philip Wong, Mohamed M. Sabry Aly, Edith Beigné, Subhasish Mitra
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. ISSCC (2019)
Mohamed M. Sabry Aly, Tony F. Wu, Andrew Bartolo, Yash H. Malviya, William Hwang, Gage Hills, Igor L. Markov, Mary Wootters, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra
The N3XT Approach to Energy-Efficient Abundant-Data Computing. Proc. IEEE 107 (1) (2019)
Haitong Li, Mudit Bhargava, Paul N. Whatmough, H.-S. Philip Wong
On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators. DAC (2019)
Connor McClellan, Andrew C. Yu, Ching-Hua Wang, H.-S. Philip Wong, Eric Pop
Vertical Sidewall MoS2 Growth and Transistors. DRC (2019)
H.-S. Philip Wong, R. Willard, Inez Kerr Bell
IC Technology - What Will the Next Node Offer Us? Hot Chips Symposium (2019)
Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Gage Hills, Bryce Hodson, William Hwang, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration. IEEE J. Solid State Circuits 53 (11) (2018)
Eilam Yalon, Kye Okabe, Christopher M. Neumann, H.-S. Philip Wong, Eric Pop
Energy-Efficient Phase Change Memory Programming by Nanosecond Pulses. DRC (2018)
William Hwang, Weier Wan, Subhasish Mitra, H.-S. Philip Wong
Coming Up N3XT, After 2D Scaling of Si CMOS. ISCAS (2018)
Gage Hills, Daniel Bankman, Bert Moons, Lita Yang, Jake Hillard, Alex Kahng, Rebecca Park, Marian Verhelst, Boris Murmann, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra
TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs. DAC (2018)
H.-S. Philip Wong
The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology. DRC (2018)
Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study. ISSCC (2018)
Ryan Zarcone, Dylan M. Paiton, Alex Anderson, Jesse H. Engel, H.-S. Philip Wong, Bruno A. Olshausen
Joint Source-Channel Coding with Neural Networks for Analog Data Compression and Storage. DCC (2018)
Abbas Rahimi, Tony F. Wu, Haitong Li, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra
Hyperdimensional Computing Nanosystem. CoRR (2018)
Stephanie M. Bohaichuk, Miguel Munoz-Rojo, Gregory Pitner, Connor McClellan, Feifei Lian, Jason Li, Jaewoo Jeong, Mahesh Samant, Stuart Parkin, H.-S. Philip Wong, Eric Pop
Low Power Nanoscale Switching of VO2using Carbon Nanotube Heaters. DRC (2018)
Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. DAC (2017)
William Hwang, Mohamed M. Sabry Aly, Yash H. Malviya, Mingyu Gao, Tony F. Wu, Christos Kozyrakis, H.-S. Philip Wong, Subhasish Mitra
abundant-data computing: special session paper. CODES+ISSS (2017)
Jesse H. Engel, Sukru Burc Eryilmaz, SangBum Kim, Matthew BrightSky, Chung Lam, Hsiang-Lan Lung, Bruno A. Olshausen, H.-S. Philip Wong
Opportunities for Analog Coding in Emerging Memory Systems. CoRR (2017)
Thomas N. Theis, H.-S. Philip Wong
The End of Moore's Law: A New Beginning for Information Technology. Comput. Sci. Eng. 19 (2) (2017)
Haitong Li, Tony F. Wu, Subhasish Mitra, H.-S. Philip Wong
Resistive RAM-Centric Computing: Design and Modeling Methodology. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Suman Datta, Alan C. Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef S. Salahuddin, Sumeet Kumar Gupta, Supratik Guha
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. DAC (2017)
Sukru Burc Eryilmaz, Emre Neftci, Siddharth Joshi, SangBum Kim, Matthew BrightSky, Hsiang-Lan Lung, Chung Lam, Gert Cauwenberghs, H.-S. Philip Wong
Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses. CoRR (2016)
Max Marcel Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra
Transforming nanodevices to next generation nanosystems. SAMOS (2016)
Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong
Neuromorphic architectures with electronic synapses. ISQED (2016)
Haitong Li, Peng Huang, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong
Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays. CoRR (2016)
Rubén Braojos, David Atienza, Mohamed M. Sabry Aly, Tony F. Wu, H.-S. Philip Wong, Subhasish Mitra, Giovanni Ansaloni
Nano-engineered architectures for ultra-low power wireless body sensor nodes. CODES+ISSS (2016)
Georges G. E. Gielen, Jelle Van Rethy, Jorge Marin, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2016)
Tony F. Wu, Karthik Ganesan, Yunqing Alexander Hu, H.-S. Philip Wong, S. Simon Wong, Subhasish Mitra
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (4) (2016)
Jinfeng Kang, Haitong Li, Peng Huang, Z. Chen, Bin Gao, Xiaoyan Liu, Zizhen Jiang, H.-S. Philip Wong
Modeling and design optimization of ReRAM. ASP-DAC (2015)
Max M. Shulaker, Tony F. Wu, Mohamed M. Sabry, Hai Wei, H.-S. Philip Wong, Subhasish Mitra
Monolithic 3D integration: a path from concept to reality. DATE (2015)
Zigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang
Contact pitch and location prediction for Directed Self-Assembly template verification. ASP-DAC (2015)
Mohamed M. Sabry, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, Mehdi Asheghi, Jeffrey Bokor, Franz Franchetti, Kenneth E. Goodson, Christos Kozyrakis, Igor L. Markov, Kunle Olukotun, Larry T. Pileggi, Eric Pop, Jan M. Rabaey, Christopher Ré, H.-S. Philip Wong, Subhasish Mitra
Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x. Computer 48 (12) (2015)
H.-S. Philip Wong, He Yi, Maryann C. Tung, Kye Okabe
Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning. ISPD (2015)
Tony F. Wu, Karthik Ganesan, Yunqing Alexander Hu, H.-S. Philip Wong, S. Simon Wong, Subhasish Mitra
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. CoRR (2015)
Sukru Burc Eryilmaz, Duygu Kuzum, Shimeng Yu, H.-S. Philip Wong
Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures. CoRR (2015)
Jinfeng Kang, Bin Gao, Peng Huang, Lifeng Liu, Xiaoyan Liu, H. Y. Yu, Shimeng Yu, H.-S. Philip Wong
RRAM based synaptic devices for neuromorphic visual systems. DSP (2015)
Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra
Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. CoRR (2015)
Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (7) (2015)
Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong
Layout optimization and template pattern verification for directed self-assembly (DSA). DAC (2015)
Georges G. E. Gielen, Jelle Van Rethy, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra
Time-based sensor interface circuits in carbon nanotube technology. ISCAS (2015)
Haitong Li, Zizhen Jiang, Peng Huang, Y. Wu, Hong-Yu Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model. DATE (2015)
Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Gnana David Jeyasingh, SangBum Kim, Matthew BrightSky, Chung Lam, H.-S. Philip Wong
Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices. CoRR (2014)
Shimeng Yu, Duygu Kuzum, H.-S. Philip Wong
Design considerations of synaptic device for neuromorphic computing. ISCAS (2014)
Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, Giovanni De Micheli
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. ACM J. Emerg. Technol. Comput. Syst. 10 (4) (2014)
Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong
Design guidelines for 3D RRAM cross-point architecture. ISCAS (2014)
Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, F. F. Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu
Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture. ISCAS (2014)
Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Gnana David Jeyasingh, SangBum Kim, Matthew BrightSky, Chung Lam, H.-S. Philip Wong
Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array. CoRR (2014)
Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang
Directed Self-Assembly (DSA) Template Pattern Verification. DAC (2014)
Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Donald M. Chiarulli, Steven P. Levitan, H.-S. Philip Wong
Video analytics using beyond CMOS devices. DATE (2014)
Gage Hills, Max M. Shulaker, Hai Wei, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra
Robust design and experimental demonstrations of carbon nanotube digital circuits. CICC (2014)
Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hai Wei, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs. IEEE J. Solid State Circuits 49 (1) (2014)
Hai Wei, Max M. Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra
Carbon nanotube circuits: opportunities and challenges. DATE (2013)
Jiale Liang, Chih-Wei Stanley Yeh, S. Simon Wong, H.-S. Philip Wong
Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array. ACM J. Emerg. Technol. Comput. Syst. 9 (1) (2013)
Daesung Lee, W. Scott Lee, Chen Chen, Farzan Fallah, J. Provine, Soogine Chong, John Watkins, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra
Combinational Logic Design Using Six-Terminal NEM Relays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Jeongha Park, Saeroonter Oh, Soyoung Kim, H.-S. Philip Wong, S. Simon Wong
Impact of III-V and Ge Devices on Circuit Performance. IEEE Trans. Very Large Scale Integr. Syst. 21 (7) (2013)
Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
Sacha: the Stanford carbon nanotube controlled handshaking robot. DAC (2013)
Gage Hills, Jie Zhang, Charles Mackin, Max M. Shulaker, Hai Wei, H.-S. Philip Wong, Subhasish Mitra
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations. DAC (2013)
Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs. ISSCC (2013)
Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma
Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. ICCAD (2013)
Rakesh Gnana David Jeyasingh, Jiale Liang, Marissa Caldwell, Duygu Kuzum, H.-S. Philip Wong
Phase Change Memory: Scaling and applications. CICC (2012)
Chen Chen, W. Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Daesung Lee, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra
Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing. ASP-DAC (2012)
Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra
Carbon Nanotube Robust Digital VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (4) (2012)
H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai
Metal-Oxide RRAM. Proc. IEEE 100 (6) (2012)
Xiangyu Chen, Jiale Liang, H.-S. Philip Wong
Interconnect scaling into the sub-10nm regime. SLIP (2012)
Chen Chen, W. Scott Lee, Roozbeh Parsa, Soogine Chong, J. Provine, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra
Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique. DATE (2012)
Jason T. Ryan, Lan Wei, Jason P. Campbell, Ricki G. Southwick, Kin P. Cheung, Anthony S. Oates, H.-S. Philip Wong, John Suehle
Circuit-aware device reliability criteria methodology. ESSCIRC (2011)
Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated. ICCAD (2011)
Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (8) (2011)
Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong
Detachable nano-carbon chip with ultra low power. DAC (2010)
Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra
Efficient FPGAs using nanoelectromechanical relays. FPGA (2010)
Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra
Carbon nanotube circuits: Living with imperfections and variations. DATE (2010)
Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, H.-S. Philip Wong
Intel LVS logic as a combinational logic paradigm in CNT technology. NANOARCH (2010)
Saeroonter Oh, Jeongha Park, S. Simon Wong, H.-S. Philip Wong
Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design. ISQED (2010)

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Publication Activity (10 Years)

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H.-S. Philip Wong