Shinobu Fujita

Publication Activity (10 Years)

Years Active: 2004-2019
Publications (10 Years): 7

Top Topics

Highly Reliable

Memory Hierarchy

Top Venues

Publications

Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami
Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications. VLSI Circuits (2019)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT (2017)
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
Physically Unclonable Function Using an Initial Waveform of Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs (7) (2017)
Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR (2017)
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
Physically Unclonable Function using Initial Waveform of Ring Oscillators. CoRR (2016)
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC (2016)
Tetsufumi Tanamoto, Naoharu Shimomura, Sumio Ikegawa, Mari Matsumoto, Shinobu Fujita, Hiroaki Yoda
High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code. CoRR (2016)
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC (2015)
Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD (2015)
Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". ASP-DAC (2014)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC (2014)
Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. VLSIC (2014)
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE (2013)
Shinobu Fujita, Kazuyoshi Hidaka
Patient Context: A New Concept for Gap Model to Understand Patient Satisfaction. ICServ (2013)
Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops (2012)
Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (1) (2011)
Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong
Detachable nano-carbon chip with ultra low power. DAC (2010)
Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA (2010)
Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. ISCAS (2010)
Shinobu Fujita
Nano-electronics challenge chip designers meet real nano-electronics in 2010s? DATE (2009)
Bipul C. Paul, Shinobu Fujita, Masaki Okajima
ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier. IEEE J. Solid State Circuits 44 (11) (2009)
Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger
CMOS vs Nano: comrades or rivals? FPGA (2009)
Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS (2009)
Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita
Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application. ISSCC (2008)
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. ICCAD (2008)
Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima
ROM based logic (RBL) design: High-performance and low-power adders. ISCAS (2008)
Toshio Mochizuki, Hiroshi Kato, Kazaru Yaegashi, Toshihisa Nishimori, Yusuke Nagamori, Shinobu Fujita
ProBoPortable: does the cellular phone software promote emergent division of labor in project-based learning? CSCL (2007)
Shinichi Yasuda, Shinobu Fujita
Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection. CICC (2007)
Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2007)
Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee
Prospect of ballistic CNFET in high performance applications: Modeling and analysis. ACM J. Emerg. Technol. Comput. Syst. 3 (3) (2007)
Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita
Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. ISVLSI (2006)
Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
3D on-chip networking technology based on post-silicon devices for future networks-on-chip. Nano-Net (2006)
Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. Nano-Net (2006)
Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee
Modeling and analysis of circuit performance of ballistic CNFET. DAC (2006)
Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita
Physical random number generators for cryptographic application in mobile devices. ESSCIRC (2005)
Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita
Physical random number generator based on MOS structure after soft breakdown. IEEE J. Solid State Circuits 39 (8) (2004)