7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
Hiroki NoguchiKazutaka IkegamiSatoshi TakayaEishi ArimaKeiichi KushidaAtsushi KawasumiHiroyuki HaraKeiko AbeNaoharu ShimomuraJunichi ItoShinobu FujitaTakashi NakadaHiroshi NakamuraPublished in: ISSCC (2016)