Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.
Hiroki NoguchiKazutaka IkegamiNaoharu ShimomuraTetsufumi TanamotoJunichi ItoShinobu FujitaPublished in: VLSIC (2014)
Keyphrases
- low power
- highly reliable
- memory access
- random access memory
- memory hierarchy
- embedded dram
- cache misses
- low power consumption
- single chip
- embedded processors
- signal processor
- low cost
- power consumption
- main memory
- high speed
- multithreading
- flash memory
- data access
- computing power
- memory management
- high power
- external memory
- memory bandwidth
- vlsi architecture
- wireless transmission
- design considerations
- digital signal processing
- memory subsystem
- shared memory
- power dissipation
- image sensor
- computer architecture
- delay insensitive
- prefetching
- vlsi circuits
- gate array
- solid state
- data storage
- processing units
- coarse grained
- power reduction
- mixed signal
- computational power
- highly efficient
- multi threaded
- file system
- end to end
- operating system
- database management systems
- data management
- nm technology
- database systems
- real time