Igor Loi

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 29

Top Topics

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Conf. Computing Frontiers

Publications

Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. CoRR (2023)
Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits 57 (1) (2022)
Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC (2021)
Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR (2021)
Jie Chen, Igor Loi, Luca Benini, Davide Rossi
Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster. DATE (2020)
Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE J. Solid State Circuits 54 (7) (2019)
Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs (8) (2018)
Martino Dazzi, Pierpaolo Palestri, Davide Rossi, Andrea Bandiziol, Igor Loi, David E. Bellasi, Luca Benini
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes. ISCAS (2018)
Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini
Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. ESSCIRC (2018)
Igor Loi, Alessandro Capotondi, Davide Rossi, Andrea Marongiu, Luca Benini
The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores. IEEE Trans. Multi Scale Comput. Syst. 4 (2) (2018)
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes. IEEE Trans. Parallel Distributed Syst. 29 (2) (2018)
Eric Flamand, Davide Rossi, Francesco Conti, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini
GAP-8: A RISC-V SoC for AI at the Edge of the IoT. ASAP (2018)
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37 (5) (2017)
Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes. CoRR (2017)
Maryam Payami, Erfan Azarkhish, Igor Loi, Luca Benini
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters. IEEE Embed. Syst. Lett. 9 (4) (2017)
Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test 34 (6) (2017)
Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR (2016)
Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. ISCAS (2016)
Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR (2016)
Giuseppe Tuveri, Paolo Meloni, Francesca Palumbo, Giovanni Pietro Seu, Igor Loi, Francesco Conti, Luigi Raffo
On-the-fly adaptivity for process networks over shared-memory platforms. Microprocess. Microsystems 46 (2016)
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips (2016)
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube. ARCS (2016)
Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision. J. Signal Process. Syst. 84 (3) (2016)
Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA. Conf. Computing Frontiers (2016)
Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. ReConFig (2016)
Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini
PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium (2015)
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
High performance AXI-4.0 based interconnect for extensible smart memory cubes. DATE (2015)
Igor Loi, Davide Rossi, Germain Haugou, Michael Gautschi, Luca Benini
Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters. Conf. Computing Frontiers (2015)
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
A Modular Shared L2 Memory Design for 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks. MES (2014)
Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
Energy-efficient vision on the PULP platform for ultra-low power parallel computing. SiPS (2014)
Davide Rossi, Igor Loi, Germain Haugou, Luca Benini
Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters. Conf. Computing Frontiers (2014)
Igor Loi, Luca Benini
A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms. DATE (2014)
Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
Online process transformation for polyhedral process networks in shared-memory MPSoCs. MECO (2014)
Mohammad Reza Kakoee, Igor Loi, Luca Benini
A shared-FPU architecture for ultra-low power MPSoCs. Conf. Computing Frontiers (2013)
Erfan Azarkhish, Igor Loi, Luca Benini
A high-performance multiported L2 memory IP for scalable three-dimensional integration. 3DIC (2013)
Erfan Azarkhish, Igor Loi, Luca Benini
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects. IET Comput. Digit. Tech. 7 (5) (2013)
Christian Weis, Igor Loi, Luca Benini, Norbert Wehn
Exploration and Optimization of 3-D Integrated DRAM Subsystems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (4) (2013)
Erfan Azarkhish, Igor Loi, Luca Benini
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters. NOCS (2013)
Christian Weis, Igor Loi, Luca Benini, Norbert Wehn
An energy efficient DRAM subsystem for 3D integrated SoCs. DATE (2012)
Mohammad Reza Kakoee, Igor Loi, Luca Benini
A resilient architecture for low latency communication in shared-L1 processor clusters. DATE (2012)
Mohammad Reza Kakoee, Igor Loi, Luca Benini
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini
Configurable Low-Latency Interconnect for Multi-core Clusters. VLSI-SoC (Selected Papers) (2012)
Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. VLSI-SoC (2012)
Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing. PATMOS (2011)
Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46 (1) (2011)
Christian Weis, Norbert Wehn, Igor Loi, Luca Benini
Design space exploration for 3D-stacked DRAMs. DATE (2011)
Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. DATE (2011)
Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (1) (2011)
Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini
3D NoCs - Unifying inter & intra chip communication. ISCAS (2010)
Mohammad Reza Kakoee, Igor Loi, Luca Benini
A new physical routing approach for robust bundled signaling on NoC links. ACM Great Lakes Symposium on VLSI (2010)
Igor Loi, Luca Benini
An efficient distributed memory interface for many-core platform with 3D stacked DRAM. DATE (2010)
Igor Loi, Federico Angiolini, Luca Benini
Synthesis of low-overhead configurable source routing tables for network interfaces. DATE (2009)
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. ICCAD (2008)
Igor Loi, Federico Angiolini, Luca Benini
Developing Mesochronous Synchronizers to Enable 3D NoCs. DATE (2008)
Paolo Meloni, Igor Loi, Federico Angiolini, Salvatore Carta, Massimo Barbaro, Luigi Raffo, Luca Benini
Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI Design 2007 (2007)
Igor Loi, Federico Angiolini, Luca Benini
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow. Nano-Net (2007)