Michele Stucchi

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 14

Top Topics

Reliability Assessment

Integrated Circuit

Injection Lasers

Solder Ball Connect

Top Venues

VLSI Technology and Circuits

Microelectron. Reliab.

Publications

Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Y. Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits (2023)
Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen
Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. ITC (2023)
Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen
Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. ETS (2023)
Anabela Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits (2022)
R. Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, A. Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits (2022)
Kristof J. P. Jacobs, Michele Stucchi, Eric Beyne
Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy. IEEE Trans. Instrum. Meas. 70 (2021)
Olalla Varela Pedreira, Michele Stucchi, Anshul Gupta, Victor Vega-Gonzalez, Marleen van der Veen, Stephane Lariviere, Christopher J. Wilson, Zsolt Tokei, Kristof Croes
Metal reliability mechanisms in Ruthenium interconnects. IRPS (2020)
Michele Stucchi, Ferenc Fodor, Erik Jan Marinissen
Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios. ETS (2020)
Kris Croes, Veerle Simons, Sofie Beyne, Vladimir Cherman, Herman Oprins, Michele Stucchi, Philippe Absil, A. Glabman, Eric Wilcox
Understanding EM-Degradation Mechanisms in Metal Heaters Used for Si Photonics Applications. IRPS (2019)
Yunlong Li, Michele Stucchi, Stefaan Van Huylenbroeck, Geert Van der Plas, Gerald Beyer, Eric Beyne, Kristof Croes
TSV process-induced MOS reliability degradation. IRPS (2018)
Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. ITC (2018)
Kristof J. P. Jacobs, T. Wang, Michele Stucchi, Mario Gonzalez, Kris Croes, Ingrid De Wolf, Eric Beyne
Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices. Microelectron. Reliab. (2017)
Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne, Mohand Brouri, Praveen Nalla, Sanjay Gopinath, Matthew Thorum, Joe Richardson, Jengyi Yu
Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. 3DIC (2016)
Kristof Croes, Joke De Messemaeker, Yunlong Li, Wei Guo, Olalla Varela Pedreira, Vladimir Cherman, Michele Stucchi, Ingrid De Wolf, Eric Beyne
Reliability Challenges Related to TSV Integration and 3-D Stacking. IEEE Des. Test 33 (3) (2016)
Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene
Impact of interconnect multiple-patterning variability on SRAMs. DATE (2015)
Yunlong Li, Stefaan Van Huylenbroeck, Els Van Besien, Xiaoping Shi, Chen Wu, Michele Stucchi, Gerald Beyer, Eric Beyne, Ingrid De Wolf, Kristof Croes
Reliability challenges for barrier/liner system in high aspect ratio through silicon vias. Microelectron. Reliab. 54 (9-10) (2014)
Michele Stucchi, Dimitrios Velenis, Guruprasad Katti
Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique. IEEE Trans. Instrum. Meas. 61 (7) (2012)
Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46 (1) (2011)
Herman Oprins, A. Srinivasan, Miroslav Cupák, Vladimir Cherman, Cristina Torregiani, Michele Stucchi, Geert Van der Plas, Paul Marchal, Bart Vandevelde, E. Cheng
Fine grain thermal modeling and experimental validation of 3D-ICs. Microelectron. J. 42 (4) (2011)
Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. CICC (2010)
Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal
3D integration: Circuit design, test, and reliability challenges. IOLTS (2010)
Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne
Design issues and considerations for low-cost 3D TSV IC technology. ISSCC (2010)
Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne
Impact of 3D design choices on manufacturing cost. 3DIC (2009)
Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne, Bart Swinnen
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). 3DIC (2009)
Paul Marchal, Bruno Bougard, Guruprasad Katti, Michele Stucchi, Wim Dehaene, Antonis Papanikolaou, Diederik Verkest, Bart Swinnen, Eric Beyne
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot. Proc. IEEE 97 (1) (2009)
Jin Guo, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor
A tool flow for predicting system level timing failures due to interconnect reliability degradation. ACM Great Lakes Symposium on VLSI (2008)
Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene
Statistically Aware SRAM Memory Array Design. ISQED (2006)
Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex
Impact of interconnect resistance increase on system performance of low power and high performance designs. SLIP (2006)
Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies. IEEE J. Solid State Circuits 41 (11) (2006)
Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex
Interconnect width selection for deep submicron designs using the table lookup method. SLIP (2004)
Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
Global interconnect trade-off for technology over memory modules to application level: case study. SLIP (2003)
Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
Interconnect exploration for future wire dominated technologies. SLIP (2002)
Michele Stucchi, Karen Maex
Frequency dependence in interline capacitance measurements. IEEE Trans. Instrum. Meas. 51 (3) (2002)
Hasan Ymeri, Bart Nauwelaers, Karen Maex, David De Roest, Michele Stucchi, Servaas Vandenberghe
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate. DATE (2002)