Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.
Giuliano SistoR. PrestonRongmei ChenGioele MirabelliAnita FarokhnejadY. ZhouIvan CiofiAnne JourdainA. VelosoMichele StucchiOdysseas ZografosPieter WeckxGeert HellingsJulien RyckaertPublished in: VLSI Technology and Circuits (2023)