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Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.

Giuliano SistoR. PrestonRongmei ChenGioele MirabelliAnita FarokhnejadY. ZhouIvan CiofiAnne JourdainA. VelosoMichele StucchiOdysseas ZografosPieter WeckxGeert HellingsJulien Ryckaert
Published in: VLSI Technology and Circuits (2023)
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