Odysseas Zografos

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 17

Top Topics

Thermal Conductivity

Higher Level Of Abstraction

Top Venues

VLSI Technology and Circuits

Publications

Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert
Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. IRPS (2024)
Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Y. Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits (2023)
Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, D. Abdi, Herman Oprins, D. Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, J. Myers, Francky Catthoor, Julien Ryckaert
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS (2023)
Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE Trans. Very Large Scale Integr. Syst. 30 (10) (2022)
Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. SLIP (2022)
Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Kristof Croes, Mustafa Badaroglu
System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents. IRPS (2022)
F. Meng, Florin Ciubotaru, S.-Y. Lee, Odysseas Zografos, M. Gupta, V. D. Nguyen, S. Couet, Gouri Sankar Kar, Giovanni De Micheli, Christoph Adelmann, I. Asselberghs
Challenges and targets of MRAM-enabled scaled spintronic logic circuits. CoRR (2022)
R. Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, A. Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits (2022)
Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert
Design enablement of CFET devices for sub-2nm CMOS nodes. DATE (2022)
Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes
A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network. SLIP (2021)
Subrat Mishra, Pieter Weckx, Odysseas Zografos, Ji-Yung Lin, Alessio Spessot, Francky Catthoor
Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm. IRPS (2021)
Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). DATE (2020)
Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken
Majority logic synthesis. ICCAD (2018)
Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli
Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies. ISVLSI (2017)
Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins
Wave pipelining for majority-based beyond-CMOS technologies. DATE (2017)
Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu
Non-volatile spin wave majority gate at the nanoscale. CoRR (2016)
Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Inversion optimization in Majority-Inverter Graphs. NANOARCH (2016)
Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubatoru, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Aaron Thean
Area and routing efficiency of SWD circuits compared to advanced CMOS. ICICDT (2015)
Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Diederik Verkest, Aaron Thean
System-level assessment and area evaluation of Spin Wave logic circuits. NANOARCH (2014)
Odysseas Zografos, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Novel grid-based power routing scheme for regular controllable-polarity FET arrangements. ISCAS (2014)
Odysseas Zografos, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli
Majority Logic Synthesis for Spin Wave Technology. DSD (2014)