Gioele Mirabelli

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 6

Top Topics

Printed Circuit

Digital Computer

Computer Interface

Computational Science

Top Venues

VLSI Technology and Circuits

Publications

S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. VLSI Technology and Circuits (2023)
Devin Verreck, Piet Wambacq, Maarten Van De Put, Zubair Ahmed, Quentin Smets, Aryan Afzalian, Rutger Duflou, Xiangyu Wu, Gioele Mirabelli, Rongmei Chen, Inge Asselberghs, Gouri Sankar Kar
The Promise of 2-D Materials for Scaled Digital and Analog Applications. ISSCC (2023)
Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Y. Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits (2023)
P. Schuddinck, F. M. Bufler, Yang Xiang, A. Farokhnejad, Gioele Mirabelli, A. Vandooren, Bilal Chehab, A. Gupta, C. Roda Neve, Geert Hellings, Julien Ryckaert
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. VLSI Technology and Circuits (2022)
Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert
Design enablement of CFET devices for sub-2nm CMOS nodes. DATE (2022)
Gioele Mirabelli, Farzan Gity, Scott Monaghan, Paul K. Hurley, Ray Duffy
Impact of impurities, interface traps and contacts on MoS2 MOSFETs: Modelling and experiments. ESSDERC (2017)