Anne Jourdain

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 7

Top Topics

Computational Science

Equivalent Circuit

High Performance Data Mining

Top Venues

VLSI Technology and Circuits

Publications

Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Y. Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits (2023)
Eric Beyne, Anne Jourdain, Gerald Beyer
Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN). VLSI Technology and Circuits (2023)
Anabela Veloso, Geert Eneman, An De Keersgieter, P. Favia, Andriy Hikavyy, R. Chen, Anne Jourdain, N. Horiguchi
Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. ICICDT (2022)
R. Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, A. Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits (2022)
K. Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, J. De Boeck, Guido Groeseneken, Julien Ryckaert, Gert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits (2022)
Jaber Derakhshandeh, Lin Hou, Inge De Preter, Carine Gerets, Samuel Suhard, Vikas Dubey, Geraldine Jamieson, Fumihiro Inoue, Tomas Webers, Pieter Bex, Giovanni Capuz, Eric Beyne, John Slabbekoorn, Teng Wang, Anne Jourdain, Gerald Beyer, Kenneth June Rebibis, Andy Miller
Die to wafer 3D stacking for below 10um pitch microbumps. 3DIC (2016)
Anne Jourdain, Joeri De Vos, Fumihiro Inoue, Kenneth J. Rebibis, Andy Miller, Gerald Beyer, Eric Beyne, Edward Walsby, Jash Patel, Oliver Ansell, Janet Hopkins, Huma Ashraf, Dave Thomas
Extreme wafer thinning optimization for via-last applications. 3DIC (2016)
Y. H. Hu, C. S. Liu, M. J. Lii, Kenneth J. Rebibis, Anne Jourdain, Antonio La Manna, Gerald Beyer, Eric Beyne, C. H. Yu
3D stacking using Cu-Cu direct bonding. 3DIC (2011)
Alain Phommahaxay, Anne Jourdain, Greet Verbinnen, Tobias Woitke, Peter Bisson, Markus Gabriel, Walter Spiess, Alice Guerrero, Jeremy McCutcheon, Rama Puligadda, Pieter Bex, Axel Van den Eede, Bart Swinnen, Gerald Beyer, Andy Miller, Eric Beyne
Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding. 3DIC (2011)
Anne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne, Youssef Travaly, Bart Swinnen
300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications. 3DIC (2010)
Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne, Bart Swinnen
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). 3DIC (2009)
Ramakanth Alapati, Youssef Travaly, Jan Van Olmen, Ricardo Cotrin Teixeira, Jan Vaes, Marc van Cauwenbergh, Anne Jourdain, Greet Verbinnen, Gino Marcuccilli, Glenn Florence, Shay Wolfling, Christine Pelissier, Haiping Zhang, Jaydeep Sinha, Andreas Machura, Irfan Malik
TSV metrology and inspection challenges. 3DIC (2009)