Mustafa Badaroglu

Publication Activity (10 Years)

Years Active: 1999-2022
Publications (10 Years): 11

Top Topics

Mobile Computing

Metal Oxide Semiconductor

Location Awareness

Top Venues

Future Gener. Comput. Syst.

Publications

Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Kristof Croes, Mustafa Badaroglu
System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents. IRPS (2022)
Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes
A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network. SLIP (2021)
Mustafa Badaroglu
Outlook of device and assembly technologies enabling high-performance mobile computing: IRDS view (invited). SLIP (2020)
Farshad Firouzi, Amir M. Rahmani, Kunal Mankodiya, Mustafa Badaroglu, Geoff V. Merrett, P. Wong, Bahar J. Farahani
Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics. Future Gener. Comput. Syst. 78 (2018)
Bahar J. Farahani, Farshad Firouzi, Victor I. Chang, Mustafa Badaroglu, Nicholas Constant, Kunal Mankodiya
Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare. Future Gener. Comput. Syst. 78 (2018)
Mustafa Badaroglu
Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond. J. Low Power Electron. 14 (2) (2018)
Jeffrey A. Smith, Kai Ni, Ram Krishna Ghosh, Jeff Xu, Mustafa Badaroglu, P. R. Chidi Chidambaram, Suman Datta
Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications. ESSDERC (2017)
Erik P. DeBenedictis, Mustafa Badaroglu, An Chen, Thomas M. Conte, Paolo A. Gargini
Sustaining Moore's Law with 3D Chips. Computer 50 (8) (2017)
Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung-Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta, David Kohen, Po-Wen Chan, Keagan Chen, P. R. Chidi Chidambaram
PPAC scaling enablement for 5nm mobile SoC technology. ESSDERC (2017)
S. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, J. Wang, G. Nallapati, Mustafa Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, Geoffrey Yeap
Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. VLSI Circuits (2016)
Mustafa Badaroglu, Jeff Xu
Interconnect-aware device targeting from PPA perspective. ICCAD (2016)
S. C. Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, J. Wang, Mustafa Badaroglu, V. Machkaoutsan, P. Narayanasetti, B. Bucki, J. Fischer, Geoffrey Yeap
Holistic technology optimization and key enablers for 7nm mobile SoC. VLSIC (2015)
Mustafa Badaroglu, Kwok Ng, Mehdi Salmani Jelodar, SungGeun Kim, Gerhard Klimeck, Chorng-Ping Chang, Charles Cheung, Yuzo Fukuzaki
More Moore landscape for system readiness - ITRS2.0 requirements. ICCD (2014)
Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. DAC (2013)
Mustafa Badaroglu, Ugur Halici, Isik Aybay, Cuneyt Cerkez
A Cascadable Random Neural Network Chip with Reconfigurable Topology. Comput. J. 53 (3) (2010)
Mustafa Badaroglu, Guy Decabooter, Francois Laulanet, Olivier Charlier
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. DATE (2008)
Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke
Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. VTC Spring (2007)
Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Scalable Gate-Level Models for Power and Timing Analysis. ISCAS (2007)
Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE J. Solid State Circuits 42 (11) (2007)
Charlotte Soens, Geert Van der Plas, Mustafa Badaroglu, Piet Wambacq, Stéphane Donnay, Yves Rolain, Maarten Kuijk
Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. IEEE J. Solid State Circuits 41 (9) (2006)
Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke
Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wirel. Commun. Netw. 2006 (2006)
Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2006)
Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. ISSCC (2006)
Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2005)
Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (1) (2005)
Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC (2004)
Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE (2004)
Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC (2004)
Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits 39 (7) (2004)
Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC (2003)
Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fonden, Svante Signell
Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. IEEE J. Solid State Circuits 38 (7) (2003)
Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. IEEE J. Solid State Circuits 37 (11) (2002)
Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC (2002)
Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. IEEE J. Solid State Circuits 37 (8) (2002)
Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE (2001)
Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens
High-level simulation of substrate noise generation including power supply noise coupling. DAC (2000)
Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels, Ivo Bolsens, Y. Zinzius, Georges G. E. Gielen, Willy Sansen, T. Fondén, Svante Signell
BANDIT: embedding analog-to-digital converters on digital telecom ASICs. ICECS (1999)