Thomas M. Conte

Publication Activity (10 Years)

Years Active: 1984-2024
Publications (10 Years): 40

Top Venues

CoRR

Computer

ICRC

ACM Trans. Archit. Code Optim.

Publications

Austin Adams, Sharjeel Khan, Jeffrey S. Young, Thomas M. Conte
Qwerty: A Basis-Oriented Quantum Programming Language. CoRR (2024)
Akihiro Hayashi, Austin Adams, Jeffrey Young, Alexander McCaskey, Eugene F. Dumitrescu, Vivek Sarkar, Thomas M. Conte
Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models. CoRR (2023)
John Vincent Atanasoff, Gordon Bell, Kiril L. Boyanov, Charles G. Call, Carl K. Chang, Thomas M. Conte, Vladimir Getov, John L. Gustafson, Hironori Kasahara, Dejan S. Milojicic, Michael R. Williams
The Invention of Electronic Digital Computing - Plenary Panel Summary. JVA (2023)
Thomas M. Conte
Status Update on the IEEE Rebooting Computing Initiative. JVA (2023)
Akihiro Hayashi, Austin Adams, Jeffrey Young, Alexander McCaskey, Eugene F. Dumitrescu, Vivek Sarkar, Thomas M. Conte
Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models. IPDPS Workshops (2023)
Sara Karamati, Clayton Hughes, K. Scott Hemmert, Ryan E. Grant, Whit Schonbein, Scott Levy, Thomas M. Conte, Jeffrey Young, Richard W. Vuduc
"Smarter" NICs for faster molecular dynamics: a case study. IPDPS (2022)
Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. IEEE Trans. Computers 71 (3) (2022)
Sara Karamati, Clayton Hughes, K. Scott Hemmert, Ryan E. Grant, Whit Schonbein, Scott Levy, Thomas M. Conte, Jeffrey Young, Richard W. Vuduc
"Smarter" NICs for faster molecular dynamics: a case study. CoRR (2022)
Austin Adams, Elton Pinto, Jeffrey Young, Creston D. Herold, Alexander J. McCaskey, Eugene F. Dumitrescu, Thomas M. Conte
Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed. ICRC (2021)
Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. ACM Trans. Archit. Code Optim. 18 (4) (2021)
Thomas M. Conte, Ian T. Foster, William Gropp, Mark D. Hill
Advancing Computing's Foundation of US Industry & Society. CoRR (2021)
Todd Hylton, Thomas M. Conte, Mark D. Hill
A vision to compute like nature: thermodynamically. Commun. ACM 64 (6) (2021)
Tong Zhou, Jun Shirako, Anirudh Jain, Sriseshan Srikanth, Thomas M. Conte, Richard W. Vuduc, Vivek Sarkar
Intrepydd: performance, productivity, and portability for data science application kernels. Onward! (2020)
Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. ACM Trans. Archit. Code Optim. 16 (4) (2020)
Michael P. Frank, Robert W. Brocato, Thomas M. Conte, Alexander H. Hsia, Anirudh Jain, Nancy A. Missert, Karpur Shukla, Brian D. Tierney
Special Session: Exploring the Ultimate Limits of Adiabatic Circuits. ICCD (2020)
Eric R. Hein, Srinivas Eswar, Abdurrahman Yasar, Jiajia Li, Jeffrey S. Young, Thomas M. Conte, Ümit V. Çatalyürek, Richard W. Vuduc, E. Jason Riedy, Bora Uçar
Programming Strategies for Irregular Algorithms on the Emu Chick. ACM Trans. Parallel Comput. 7 (4) (2020)
Eric R. Hein, Srinivas Eswar, Abdurrahman Yasar, Jiajia Li, Jeffrey S. Young, Thomas M. Conte, Ümit V. Çatalyürek, Rich Vuduc, E. Jason Riedy, Bora Uçar
Programming Strategies for Irregular Algorithms on the Emu Chick. CoRR (2019)
Will Powell, E. Jason Riedy, Jeffrey S. Young, Thomas M. Conte
Wrangling Rogues: A Case Study on Managing Experimental Post-Moore Architectures. PEARC (2019)
Vladimir Getov, Peter M. Kogge, Thomas M. Conte
Application Performance of Physical System Simulations. PARCO (2019)
Jeffrey S. Young, E. Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, Sriseshan Srikanth
Experimental Insights from the Rogues Gallery. ICRC (2019)
Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang
Tackling memory access latency through DRAM row management. MEMSYS (2018)
Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
Extending Moore's Law via Computationally Error-Tolerant Computing. ACM Trans. Archit. Code Optim. 15 (1) (2018)
Thomas M. Conte, Erik P. DeBenedictis, Avi Mendelson, Dejan S. Milojicic
Rebooting Computers to Avoid Meltdown and Spectre. Computer 51 (4) (2018)
F. D. Wright, Thomas M. Conte
Standards: Roadmapping Computer Technology Trends Enlightens Industry. Computer 51 (6) (2018)
Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA (2018)
Onur Mutlu, Scott A. Mahlke, Thomas M. Conte, Wen-Mei W. Hwu
Iterative Modulo Scheduling. IEEE Micro 38 (1) (2018)
Thomas M. Conte, Erik P. DeBenedictis, Paolo A. Gargini, Elie K. Track
Rebooting Computing: The Road Ahead. Computer 50 (1) (2017)
Jeffrey S. Vetter, Erik P. DeBenedictis, Thomas M. Conte
Architectures for the Post-Moore Era. IEEE Micro 37 (4) (2017)
Erik P. DeBenedictis, Mustafa Badaroglu, An Chen, Thomas M. Conte, Paolo A. Gargini
Sustaining Moore's Law with 3D Chips. Computer 50 (8) (2017)
Thomas M. Conte, Erik P. DeBenedictis, R. Stanley Williams, Mark D. Hill
Challenges to Keeping the Computer Industry Centered in the US. CoRR (2017)
Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. ICRC (2017)
Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. HPEC (2017)
Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
Computationally-redundant energy-efficient processing for y'all (CREEPY). ICRC (2016)
Rishiraj A. Bheda, Thomas M. Conte, Jeffrey S. Vetter
Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging. MEMSYS (2016)
Sriseshan Srikanth, Bobin Deng, Thomas M. Conte
A Brief Survey of Non-Residue Based Computational Error Correction. CoRR (2016)
Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte
Energy efficiency limits of logic and memory. ICRC (2016)
Yung-Hsiang Lu, Alan M. Kadin, Alexander C. Berg, Thomas M. Conte, Erik P. DeBenedictis, Rachit Garg, Ganesh Gingade, Bichlien Hoang, Yongzhen Huang, Boxun Li, Jingyu Liu, Wei Liu, Huizi Mao, Junran Peng, Tianqi Tang, Elie K. Track, Jingqiu Wang, Tao Wang, Yu Wang, Jun Yao
Rebooting Computing and Low-Power Image Recognition Challenge. ICCAD (2015)
Thomas M. Conte
The Computer Society Must Change. Computer 48 (12) (2015)
Brian P. Railing, Eric R. Hein, Thomas M. Conte
Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Thomas M. Conte, Elie K. Track, Erik DeBenedictis
Rebooting Computing: New Strategies for Technology Scaling. Computer 48 (12) (2015)
Jesse G. Beu, Jason A. Poovey, Eric R. Hein, Thomas M. Conte
High-speed formal verification of heterogeneous coherence hierarchies. HPCA (2013)
Paul D. Bryan, Jason A. Poovey, Jesse G. Beu, Thomas M. Conte
Accelerating Multi-threaded Application Simulation through Barrier-Interval Time-Parallelism. MASCOTS (2012)
Rishiraj A. Bheda, Jesse G. Beu, Brian P. Railing, Thomas M. Conte
Extrapolation Pitfalls When Evaluating Limited Endurance Memory. MASCOTS (2012)
Jesse G. Beu, Michel C. Rosier, Thomas M. Conte
Manager-client pairing: a framework for implementing coherence hierarchies. MICRO (2011)
Rishiraj A. Bheda, Jason A. Poovey, Jesse G. Beu, Thomas M. Conte
Energy efficient Phase Change Memory based main memory for future high performance systems. IGCC (2011)
Jason A. Poovey, Brian P. Railing, Thomas M. Conte
Parallel Pattern Detection for Architectural Improvements. HotPar (2011)
Jason A. Poovey, Thomas M. Conte, Markus Levy, Shay Gal-On
A Benchmark Characterization of the EEMBC Benchmark Suite. IEEE Micro 29 (5) (2009)
Balaji V. Iyer, Thomas M. Conte
On power and energy trends of IEEE 802.11n PHY. MSWiM (2009)
Markus Levy, Thomas M. Conte
Embedded Multicore Processors and Systems. IEEE Micro 29 (3) (2009)
Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
Energy-aware opcode design. ICCD (2008)
Balaji V. Iyer, Thomas M. Conte
A Power Model for Register-Sharing Structures. DIPES (2008)
Thomas M. Conte
Keynote: Insight, Not (Random) Numbers: An Embedded Perspective. HiPEAC (2007)
Paul D. Bryan, Michel C. Rosier, Thomas M. Conte
Reverse State Reconstruction for Sampled Microarchitectural Simulation. ISPASS (2007)
Paul D. Bryan, Thomas M. Conte
Combining cluster sampling with single pass methods for efficient sampling regimen design. ICCD (2007)
Emre Özer, Thomas M. Conte
High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. IEEE Trans. Parallel Distributed Syst. 16 (12) (2005)
Monther Aldwairi, Thomas M. Conte, Paul D. Franzon
Configurable string matching hardware for speeding up intrusion detection. SIGARCH Comput. Archit. News 33 (1) (2005)
Thomas M. Conte
Insight, not (random) numbers. ISPASS (2005)
Huiyang Zhou, Thomas M. Conte
Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. IEEE Trans. Computers 54 (7) (2005)
Saurabh Sharma, Jesse G. Beu, Thomas M. Conte
Spectral prefetcher: An effective mechanism for L2 cache prefetching. ACM Trans. Archit. Code Optim. 2 (4) (2005)
Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete
Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. IEEE Micro 24 (4) (2004)
Chao-ying Fu, Jill T. Bodine, Thomas M. Conte
Modeling Value Speculation: An Optimal Edge Selection Problem. IEEE Trans. Computers 52 (3) (2003)
Huiyang Zhou, Jill Flanagan, Thomas M. Conte
Detecting Global Stride Locality in Value Streams. ISCA (2003)
Huiyang Zhou, Thomas M. Conte
Enhancing memory level parallelism via recovery-free value prediction. ICS (2003)
Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embed. Comput. Syst. 2 (3) (2003)
Thomas M. Conte
Choosing the Brain(s) of an Embedded System. Computer 35 (7) (2002)
Huiyang Zhou, Thomas M. Conte
Code Size Efficiency in Global Scheduling for ILP Processors. Interaction between Compilers and Computer Architectures (2002)
Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte
Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. LCPC (2001)
Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT (2001)
Emre Özer, Thomas M. Conte, Saurabh Sharma
Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. HiPC (2001)
Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. Very Large Scale Integr. Syst. 8 (2) (2000)
Kim M. Hazelwood, Thomas M. Conte
A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. IEEE PACT (2000)
Thomas M. Conte, Sumedh W. Sathaye
Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. IEEE Trans. Computers 49 (8) (2000)
Sergei Y. Larin, Thomas M. Conte
Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. MICRO (1999)
Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte
Dynamically Programmable Cache Evaluation and Virtualization. FPGA (1999)
Pradip Bose, Thomas M. Conte, Todd M. Austin
Challenges in processor modeling and validation [Guest Editors?? introduction]. IEEE Micro 19 (3) (1999)
Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman
Editors' Introduction. Int. J. Parallel Program. 27 (6) (1999)
Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman
Editor's Introduction. Int. J. Parallel Program. 27 (5) (1999)
Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte
Value Speculation Scheduling for High Performance Processors. ASPLOS (1998)
William A. Havanki, Sanjeev Banerjia, Thomas M. Conte
Treegion Scheduling for Wide Issue Processors. HPCA (1998)
Pradip Bose, Thomas M. Conte
Performance Analysis and Its Impact on Design. Computer 31 (5) (1998)
Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte
MPS: Miss-Path Scheduling for Multiple-Issue Processors. IEEE Trans. Computers 47 (12) (1998)
Emre Özer, Sanjeev Banerjia, Thomas M. Conte
Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. MICRO (1998)
Matthew D. Jennings, Thomas M. Conte
Subword extensions for video processing on mobile systems. IEEE Concurr. 6 (3) (1998)
Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte
A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT (1998)
Thomas M. Conte, Mary Ann Hirsch, Wen-mei W. Hwu
Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation. IEEE Trans. Computers 47 (6) (1998)
Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe
Challenges to Combining General-Purpose and Multimedia Processors. Computer 30 (12) (1997)
Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte
Path Prediction for High Issue-Rate Processors. IEEE PACT (1997)
Thomas M. Conte, Sumedh W. Sathaye
Optimization of VLIW compatibility systems employing dynamic rescheduling. Int. J. Parallel Program. 25 (2) (1997)
Sanjeev Banerjia, William A. Havanki, Thomas M. Conte
Treegion Scheduling for Highly Parallel Processors. Euro-Par (1997)
Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson
Compilers for Instruction-Level Parallelism. Computer 30 (12) (1997)
Thomas M. Conte, Andrew Wolfe
Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities. HICSS (1) (1997)
Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes
Reducing State Loss For Effective Trace Sampling of Superscalar Processors. ICCD (1996)
Ashutosh Singla, Thomas M. Conte
Bipartitioning for Hybrid FPGA-Software Simulatio. VLSI Design (1996)
Thomas M. Conte
Importance of Profiling and Compatibility. ACM Comput. Surv. 28 (4es) (1996)
Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch
Accurate and Practical Profile-driven Compilation Using the Profile Buffer. MICRO (1996)
Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. MICRO (1996)
Thomas M. Conte, Burzin A. Patel, Kishore N. Menezes, J. Stan Cox
Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization. Int. J. Parallel Program. 24 (2) (1996)
Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia
A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. MICRO (1996)
J. Stan Cox, David P. Howell, Thomas M. Conte
Commercializing profile-driven optimization. HICSS (1) (1995)
Thomas M. Conte, Wen-mei W. Hwu
Advances in Benchmarking Techniques: New Standards and Quantitative Metrics. Adv. Comput. 41 (1995)

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Publication Activity (10 Years)

Top Topics

Top Venues

Thomas M. Conte