Sriseshan Srikanth

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 15

Top Topics

Ultra Low Power

Top Venues

ACM Trans. Archit. Code Optim.

Publications

Armand Behroozi, Yuxiang Chen, Vlad Fruchter, Lavanya Subramanian, Sriseshan Srikanth, Scott A. Mahlke
SlimSLAM: An Adaptive Runtime for Visual-Inertial Simultaneous Localization and Mapping. ASPLOS (3) (2024)
Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. IEEE Trans. Computers 71 (3) (2022)
Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. ACM Trans. Archit. Code Optim. 18 (4) (2021)
Tong Zhou, Jun Shirako, Anirudh Jain, Sriseshan Srikanth, Thomas M. Conte, Richard W. Vuduc, Vivek Sarkar
Intrepydd: performance, productivity, and portability for data science application kernels. Onward! (2020)
Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. ACM Trans. Archit. Code Optim. 16 (4) (2020)
Jeffrey S. Young, E. Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, Sriseshan Srikanth
Experimental Insights from the Rogues Gallery. ICRC (2019)
Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang
Tackling memory access latency through DRAM row management. MEMSYS (2018)
Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
Extending Moore's Law via Computationally Error-Tolerant Computing. ACM Trans. Archit. Code Optim. 15 (1) (2018)
Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA (2018)
Anirudh Jain, Sriseshan Srikanth, Erik P. DeBenedictis, Tushar Krishna
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip. ICRC (2018)
Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. ICRC (2017)
Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. HPEC (2017)
Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
Computationally-redundant energy-efficient processing for y'all (CREEPY). ICRC (2016)
Sriseshan Srikanth, Bobin Deng, Thomas M. Conte
A Brief Survey of Non-Residue Based Computational Error Correction. CoRR (2016)
Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte
Energy efficiency limits of logic and memory. ICRC (2016)