Jeanine E. Cook

Publication Activity (10 Years)

Years Active: 2002-2022
Publications (10 Years): 28

Top Topics

Energy Efficiency

Monte Carlo Methods

Transactional Memory

General Purpose Processors

Top Venues

ACM Trans. Archit. Code Optim.

Publications

Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. IEEE Trans. Computers 71 (3) (2022)
Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. ACM Trans. Archit. Code Optim. 18 (4) (2021)
Daniel Dunning, Robert W. Robey, Jeffery Kuehn, Jeanine E. Cook
A Performance Analysis of Phantom-Cell Adaptive Mesh Refinement on CPUs and GPUs. J. Comput. Inf. Sci. Eng. 21 (1) (2021)
Richard F. Barrett, Jeanine E. Cook, Stephen L. Olivier, Omar Aaziz, Christipher D. Jenkins, Courtenay T. Vaughan
Exploring Chapel Productivity Using Some Graph Algorithms. IPDPS Workshops (2020)
Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. ACM Trans. Archit. Code Optim. 16 (4) (2020)
Omar Aaziz, Jeanine E. Cook, Courtenay Vaughan, David Richards
Proxy or Imposter? A Method and Case Study to Determine the Answer. CLUSTER (2019)
Omar Aaziz, Courtenay Vaughan, Jonathan Cook, Jeanine E. Cook, Jeffery Kuehn, David Richards
Fine-Grained Analysis of Communication Similarity between Real and Proxy Applications. PMBS@SC (2019)
Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
Extending Moore's Law via Computationally Error-Tolerant Computing. ACM Trans. Archit. Code Optim. 15 (1) (2018)
Omar Aaziz, Jeanine E. Cook, Jonathan Cook, Courtenay Vaughan
Exploring and Quantifying How Communication Behaviors in Proxies Relate to Real Applications. PMBS@SC (2018)
Nafiul Alam Siddique, Patricia Grubel, Abdel-Hameed A. Badawy, Jeanine E. Cook
A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC. J. Supercomput. 74 (2) (2018)
Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA (2018)
Omar Aaziz, Jeanine E. Cook, Jonathan Cook, Tanner Juedeman, David Richards, Courtenay Vaughan
A Methodology for Characterizing the Correspondence Between Real and Proxy Applications. CLUSTER (2018)
Nafiul Alam Siddique, Abdel-Hameed A. Badawy, Jeanine E. Cook, David Resnick
Local memory store (LMStr): A hardware controlled shared scratchpad for multicores. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI (2017)
Li Tang, Richard F. Barrett, Jeanine E. Cook, Xiaobo Sharon Hu
PeaPaw: Performance and Energy-Aware Partitioning of Workload on Heterogeneous Platforms. ACM Trans. Design Autom. Electr. Syst. 22 (3) (2017)
Mohammad A. Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook
Analyzing Hybrid Transactional Memory Performance Using Intel SDE. CLUSTER (2017)
Mohammad Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook
DAdHTM: Low overhead dynamically adaptive hardware transactional memory for large graphs a scalability study. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI (2017)
Nafiul Alam Siddique, Abdel-Hameed A. Badawy, Jeanine E. Cook, David Resnick
LMStr: exploring shared hardware controlled scratchpad memory for multicores. MEMSYS (2017)
Mohammad A. Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook
StAdHyTM: A Statically Adaptive Hybrid Transactional Memory: A scalability study on large parallel graphs. CCWC (2017)
Mohammad Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook
DyAdHyTM: A Low Overhead Dynamically Adaptive Hybrid Transactional Memory on Big Data Graphs. CoRR (2017)
Mohammad A. Qayum, Abdel-Hameed A. Badawy, Jeanine E. Cook
DyAdHyTM: a low overhead dynamically adaptive hybrid transactional memory with application to large graphs. MEMSYS (2017)
Xingfu Wu, Valerie E. Taylor, Jeanine E. Cook, Tanner Juedeman
Performance and Power Characteristics and Optimizations of Hybrid MPI/OpenMP LULESH Miniapps under Various Workloads. E2SC@SC (2017)
Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. ICRC (2017)
Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. HPEC (2017)
Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
Computationally-redundant energy-efficient processing for y'all (CREEPY). ICRC (2016)
Patricia Grubel, Hartmut Kaiser, Kevin A. Huck, Jeanine E. Cook
Using Intrinsic Performance Counters to Assess Efficiency in Task-Based Parallel Applications. IPDPS Workshops (2016)
Nafiul Alam Siddique, Abdel-Hameed A. Badawy, Jeanine E. Cook, David Resnick
LMStr: Local memory store the case for hardware controlled scratchpad memory for general purpose processors. IPCCC (2016)
Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte
Energy efficiency limits of logic and memory. ICRC (2016)
Xingfu Wu, Valerie E. Taylor, Jeanine E. Cook, Philip J. Mucci
Using Performance-Power Modeling to Improve Energy Efficiency of HPC Applications. Computer 49 (10) (2016)
Erik P. DeBenedictis, Jeanine E. Cook, Mark Hoemmen, Tzevetan S. Metodi
Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS). NANOARCH (2015)
Patricia Grubel, Hartmut Kaiser, Jeanine E. Cook, Adrian Serio
The Performance Implication of Task Size for Applications on the HPX Runtime System. CLUSTER (2015)
J. A. Ang, Richard F. Barrett, R. E. Benner, D. Burke, C. Chan, Jeanine E. Cook, David Donofrio, Simon D. Hammond, Karl S. Hemmert, S. M. Kelly, H. Le, Vitus J. Leung, David R. Resnick, Arun F. Rodrigues, John Shalf, Dylan T. Stark, Didem Unat, Nicholas J. Wright
Abstract machine models and proxy architectures for exascale computing. Co-HPC@SC (2014)
Waleed Alkohlani, Jeanine E. Cook, Jonathan Cook
Accurate statistical performance modeling and validation of out-of-order processors using Monte Carlo methods. IPCCC (2014)
Waleed Alkohlani, Jeanine E. Cook, Nafiul Siddique
Insight into Application Performance Using Application-Dependent Characteristics. PMBS@SC (2014)
Mustafa Elfituri, Jeanine E. Cook, Jonathan Cook
Binary instrumentation support for measuring performance in OpenMP programs. SE-CSE@ICSE (2013)
Waleed Alkohlani, Jeanine E. Cook
Towards Performance Predictive Application-Dependent Workload Characterization. SC Companion (2012)
Jeanine E. Cook, Jonathan Cook, Waleed Alkohlani
A statistical performance model of the opteron processor. SIGMETRICS Perform. Evaluation Rev. 38 (4) (2011)
Waleed Alkohlani, Jeanine E. Cook, Ram Srinivasan
Extending the Monte Carlo Processor Modeling Technique: Statistical Performance Models of the Niagara 2 Processor. ICPP (2010)
Santosh Talli, Ram Srinivasan, Jeanine E. Cook
Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization. IPCCC (2007)
Ram Srinivasan, Eitan Frachtenberg, Olaf M. Lubeck, Scott Pakin, Jeanine E. Cook
An Idealistic Neuro-PPM Branch Predictor. J. Instr. Level Parallelism 9 (2007)
Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck
Performance modeling using Monte Carlo simulation. IEEE Comput. Archit. Lett. 5 (1) (2006)
Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach. SBAC-PAD (2006)
Ram Srinivasan, Jeanine E. Cook, Shaun Cooper
Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection. ISPASS (2005)
Wiplove Mathur, Jeanine E. Cook
Improved Estimation for Software Multiplexing of Performance Counters. MASCOTS (2005)
Jeanine E. Cook, Richard L. Oliver, Eric E. Johnson
Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity. SIGMETRICS (2002)