Tackling memory access latency through DRAM row management.

Sriseshan Srikanth Lavanya Subramanian Sreenivas Subramoney Thomas M. Conte Hong Wang

Published in: MEMSYS (2018)

Keyphrases

access latency
main memory
memory access
prefetching
cache hit ratio
management system
high density
scheduling algorithm
memory subsystem
index structure
data structure
random access
data access
database
access patterns
data retrieval
data broadcast
random access memory
ibm zenterprise
data management