Eric Rotenberg

Publication Activity (10 Years)

Years Active: 1996-2021
Publications (10 Years): 13

Top Topics

Physical Design

Memory Hierarchy

Multi Core Processors

Top Venues

Publications

Chanchal Kumar, Anirudh Seshadri, Aayush Chaudhary, Shubham Bhawalkar, Rohit Singh, Eric Rotenberg
Post-Fabrication Microarchitecture. MICRO (2021)
Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Eric Rotenberg
Slipstream Processors Revisited: Exploiting Branch Sets. ISCA (2020)
Chanchal Kumar, Aayush Chaudhary, Shubham Bhawalkar, Utkarsh Mathur, Saransh Jain, Adith Vastrad, Eric Rotenberg
Post-Silicon Microarchitecture. IEEE Comput. Archit. Lett. 19 (1) (2020)
Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor. ICCD (2017)
Sungkwan Ku, Elliott Forbes, Rangeen Basu Roy Chowdhury, Eric Rotenberg
A case for standard-cell based RAMs in highly-ported superscalar processor structures. ISQED (2017)
Elliott Forbes, Eric Rotenberg
Fast register consolidation and migration for heterogeneous multi-core processors. ICCD (2016)
Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Eric Rotenberg
AnyCore-1: A comprehensively adaptive 4-way superscalar processor. Hot Chips Symposium (2016)
Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Sungkwan Ku, Eric Rotenberg
AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores. ISPASS (2016)
Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
Physical design of a 3D-stacked heterogeneous multi-core processor. 3DIC (2016)
Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Steve Lipa
Computing in 3D. CICC (2015)
Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa
Computing in 3D. 3DIC (2015)
Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. Hot Chips Symposium (2015)
Rami Sheikh, James Tuck, Eric Rotenberg
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching. IEEE Trans. Computers 64 (8) (2015)
Paul D. Franzon, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel
3D-enabled customizable embedded computer (3DECC). 3DIC (2014)
Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. ASP-DAC (2014)
Elliott Forbes, Niket Kumar Choudhary, Brandon H. Dwiel, Eric Rotenberg
Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores. ICCD (2014)
Nyunyi M. Tshibangu, Paul D. Franzon, Eric Rotenberg, William Rhett Davis
Design of controller for L2 cache mapped in Tezzaron stacked DRAM. 3DIC (2013)
Sandeep Navada, Niket K. Choudhary, Salil V. Wadhavkar, Eric Rotenberg
A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors. PACT (2013)
Shivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis, Paul D. Franzon
3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors. ISQED (2013)
Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon
Rationale for a 3D heterogeneous multi-core processor. ICCD (2013)
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg
FabScalar: Automating Superscalar Core Design. IEEE Micro 32 (3) (2012)
Brandon H. Dwiel, Niket Kumar Choudhary, Eric Rotenberg
FPGA modeling of diverse superscalar processors. ISPASS (2012)
Rami Sheikh, James Tuck, Eric Rotenberg
Control-Flow Decoupling. MICRO (2012)
Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg
A physical design study of fabscalar-generated superscalar cores. VLSI-SoC (2012)
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. ISCA (2011)
Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg
EXACT: explicit dynamic-branch prediction with active updates. Conf. Computing Frontiers (2010)
Sandeep Navada, Niket Kumar Choudhary, Eric Rotenberg
Criticality-driven superscalar design space exploration. PACT (2010)
Hashem Hashemi Najaf-abadi, Eric Rotenberg
The importance of accurate task arrival characterization in the design of processing cores. IISWC (2009)
Hashem Hashemi Najaf-abadi, Eric Rotenberg
Architectural Contesting. HPCA (2009)
Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary, Eric Rotenberg
Core-Selectability in Chip Multiprocessors. PACT (2009)
Vimal K. Reddy, Eric Rotenberg
Coverage of a microarchitecture-level fault check regimen in a superscalar processor. DSN (2008)
Hashem Hashemi Najaf-abadi, Eric Rotenberg
Configurational Workload Characterization. ISPASS (2008)
Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary
Transparent control independence (TCI). ISCA (2007)
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. IEEE Trans. Computers 56 (2) (2007)
Vimal K. Reddy, Eric Rotenberg
Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. DSN (2007)
Hashem Hashemi Najaf-abadi, Eric Rotenberg
: exposing and exploiting temperamental behavior. SIGARCH Comput. Archit. News 35 (3) (2007)
Aravindh Anantaraman, Eric Rotenberg
Non-uniform program analysis & repeatable execution constraints: exploiting out-of-order processors in real-time systems. SIGBED Rev. 3 (1) (2006)
Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg
FAST: Frequency-aware static timing analysis. ACM Trans. Embed. Comput. Syst. 5 (1) (2006)
Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi
Assertion-Based Microarchitecture Design for Improved Reliability. ICCD (2006)
Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. HPCA (2006)
Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. ASPLOS (2006)
Eric Rotenberg, Ravi V. Venkatesan
The State of ZettaRAM. Nano-Net (2006)
Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. CASES (2005)
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg
for Low-Power Memory Systems. HPCA (2005)
Ali El-Haj-Mahmoud, Eric Rotenberg
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. CASES (2004)
Jinson Koppanalil, Eric Rotenberg
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. IEEE Trans. Computers 53 (4) (2004)
Aravindh Anantaraman, Kiran Seth, Eric Rotenberg, Frank Mueller
Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). RTSS (2004)
Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg
Slipstream Execution Mode for CMP-Based Multiprocessors. HPCA (2003)
Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg
FAST: Frequency-Aware Static Timing Analysis. RTSS (2003)
Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embed. Comput. Syst. 2 (3) (2003)
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. ISCA (2003)
Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg
A case for dynamic pipeline scaling. CASES (2002)
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan
A Large, Fast Instruction Window for Tolerating Cache Misses. ISCA (2002)
Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT (2001)
Eric Rotenberg
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. MICRO (2001)
Eric Rotenberg, James E. Smith
Control Independence in Trace Processors. J. Instr. Level Parallelism 2 (2000)
Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg
Slipstream Processors: Improving both Performance and Fault Tolerance. ASPLOS (2000)
Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg
A study of slipstream processors. MICRO (2000)
Eric Rotenberg, Steve Bennett, James E. Smith
A Trace Cache Microarchitecture and Evaluation. IEEE Trans. Computers 48 (2) (1999)
Eric Rotenberg, Quinn Jacobson, James E. Smith
A Study of Control Independence in Superscalar Processors. HPCA (1999)
Eric Rotenberg
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. FTCS (1999)
Eric Rotenberg, James E. Smith
Control Independence in Trace Processors. MICRO (1999)
Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
Trace Processors. MICRO (1997)
Quinn Jacobson, Eric Rotenberg, James E. Smith
Path-Based Next Trace Prediction. MICRO (1997)
Erik Jacobsen, Eric Rotenberg, James E. Smith
Assigning Confidence to Conditional Branch Predictions. MICRO (1996)
Eric Rotenberg, Steve Bennett, James E. Smith
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. MICRO (1996)