Toshio Kondo

Publication Activity (10 Years)

Years Active: 1985-2018
Publications (10 Years): 7

Top Topics

Design Automation

Garbage Collection

Top Venues

IET Comput. Digit. Tech.

Publications

BaoKang Wang, Yuki Fukazawa, Toshio Kondo, Takahiro Sasaki
Tile/line access cache memory based on a multi-level Z-order tiling data layout. Concurr. Comput. Pract. Exp. 30 (9) (2018)
BaoKang Wang, Yuki Fukazawa, Toshio Kondo, Takahiro Sasaki
A cache memory with unit tile and line accessibility. HPCS (2016)
Yuki Fukazawa, Keita Watanabe, Yuki Minoura, Toshio Kondo, Takahiro Sasaki
SIMD-based datapath with efficient operation structure for motion estimation. ICASSP (2016)
Kouki Kayamuro, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo
A Rapid Verification Framework for Developing Multi-core Processor. CANDAR (2016)
BaoKang Wang, Yuki Fukazawa, Toshio Kondo, Takahiro Sasaki
A cache memory with unit tile and line accessibility. ICIS (2016)
Hiroaki Kawashima, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo
Register Port Prediction for a Banked Register File. CANDAR (2015)
Seiji Miyoshi, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo
An Architectural Framework of Snoopy Interconnection for Heterogeneous Cache Systems. CANDAR (2015)
Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. ASP-DAC (2014)
Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
Detail Design and Evaluation of Fab Cache. CANDAR (2014)
Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
Dynamic BTB Resizing for Variable Stages Superscalar Architecture. CANDAR (2013)
Tomoyuki Nakabayashi, Takahiro Sasaki, Hitoshi Nakamura, Kazuhiko Ohno, Toshio Kondo
Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip. Int. J. Netw. Comput. 3 (2) (2013)
Takahiro Sasaki, Tomoyuki Nakabayashi, Kazumasa Nomura, Kazuhiko Ohno, Toshio Kondo
Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor. IET Comput. Digit. Tech. 7 (1) (2013)
Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo
FabCache: Cache Design Automation for Heterogeneous Multi-core Processors. CANDAR (2013)
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture. ICNC (2012)
Tomoyuki Nakabayashi, Takahiro Sasaki, I. K. Ohno, Toshio Kondo
Design and evaluation of variable stages pipeline processor with low-energy techniques. IET Comput. Digit. Tech. 6 (1) (2012)
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Design and evaluation of variable stages pipeline processor chip. ASP-DAC (2011)
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Low power semi-static TSPC D-FFs using split-output latch. ISOCC (2011)
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Design and Evaluation of Variable Stages Pipeline Processor Chip. ISIA (2010)
Nobuyuki Matsubara, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo
Evaluation of Variable Level Cache. ISIA (2010)
Takahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo
Evaluation of low-energy and high-performance processor using variable stages pipeline technique. IET Comput. Digit. Tech. 2 (3) (2008)
Wujian Zhang, Runde Zhou, Toshio Kondo
Low-power motion-estimation architecture based on a novel early-jump-out technique. ISCAS (5) (2001)
Tsuneo Okubo, Mitsuo Ikeda, Yutaka Tashiro, Toshio Kondo, Ryota Kasai, Hiroshi Kotera, Tetsuma Sakurai
Concurrent and collaborative methodologies in short TAT LSI design and manufacturing. Systems and Computers in Japan 30 (7) (1999)
Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai
SuperENC: MPEG-2 video encoder chip. IEEE Micro 19 (4) (1999)
Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. DATE (1999)
Kazuhito Suguri, Toshihiro Minami, Hiroaki Matsuda, Ritsu Kusaba, Toshio Kondo, Ryota Kasai, Takumi Watanabe, Hidenuri Sato, Nobutarou Shibata, Yutaka Tashiro, Takaaki Izuoka, Atsushi Shimizu, Hiroshi Kotera
A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding. IEEE J. Solid State Circuits 31 (11) (1996)
Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato
Two-chip MPEG-2 video encoder. IEEE Micro 16 (2) (1996)
Toshio Kondo, Yoshi Sugiyama, Takayoshi Nakashima
Two-Dimensional Array Processor AAP2 and Its Programming Language. Systems and Computers in Japan 20 (12) (1989)
Kenichi Nishide, Moritomo Hanawa, Toshio Kondo
Automatic position findings of vehicle by means of laser. ICRA (1986)
Toshio Kondo, Toshio Tsuchiya, Yoshihiro Kitamura, Yoshi Sugiyama, Takashi Kimura, Takayoshi Nakashima
Pseudo MIMD Array Processor - AAP2. ISCA (1986)
Toshio Kondo, Tayoshi Nakashima, Toshio Tsuchiya, Yoshi Sugiyama, Tsuneta Sudo
A large scale cellular array processor: AAP-1. ACM Conference on Computer Science (1985)