Tsuneta Sudo

Publication Activity (10 Years)

Years Active: 1981-1988
Publications (10 Years): 0

Publications

Tohru Adachi, M. Tanno, Tsuneta Sudo
Software Environment for 500 MHz VLSI Test System "ULTIMATE". ITC (1988)
Teruo Tamama, Naoaki Narumi, Taiichi Otsuji, Masao Suzuki, Tsuneta Sudo
Key Technologies for 500 MHz VLSI Test System "ULTIMATE". ITC (1988)
Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo
Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE". ITC (1988)
Tsuneta Sudo
Design automation systems in Japan. IEEE Des. Test 5 (6) (1988)
Toshio Kondo, Tayoshi Nakashima, Toshio Tsuchiya, Yoshi Sugiyama, Tsuneta Sudo
A large scale cellular array processor: AAP-1. ACM Conference on Computer Science (1985)
Kiyoyuki Yokoyama, Masaaki Tomizawa, Akira Yoshii, Tsuneta Sudo
Semiconductor Device Simulation at NTT. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 (4) (1985)
Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo
Hierarchical top-down layout design method for VLSI chip. DAC (1982)
Shigeru Sugamori, Kenji Yoshida, Hiromi Maruyama, Shinpei Kamata, Tsuneta Sudo
Analysis and Definition of Overall Timing Accuracy in VLSI Test System. ITC (1981)