Tohru Adachi

Publication Activity (10 Years)

Years Active: 1982-2021
Publications (10 Years): 1

Top Topics

Weakly Supervised

Highly Efficient

Unsupervised Feature Learning

Top Venues

Publications

Ken Namura, Johannes Maximilian Kühn, Tohru Adachi, H. Imachi, H. Kaneko, T. Kato, Go Watanabe, Naoto Tanaka, S. Kashihara, Hiroshi Miyashita, Y. Tomonaga, Ryosuke Okuta, Takuya Akiba, Brian Vogel, S. Kitajo, F. Osawa, K. Takahashi, Y. Takatsukasa, K. Mizumaru, T. Yamauchi, J. Ono, A. Takahashi, Tanvir Ahmed, Y. Doi, K. Hiraki, J. Makino
MN-Core - A Highly Efficient and Scalable Approach to Deep Learning. VLSI Circuits (2021)
Tohru Adachi, M. Tanno, Tsuneta Sudo
Software Environment for 500 MHz VLSI Test System "ULTIMATE". ITC (1988)
Kazuhiro Ueda, Hitoshi Kitazawa, Tohru Adachi, Ikuo Harada
Top-Down Layout for Hierarchical Custom Design. IEEE Des. Test 4 (6) (1987)
Hiroshi Miyashita, Tohru Adachi, Kazuhiro Ueda
An automatic cell pattern generation system for CMOS transistor-pair array LSI. Integr. 4 (2) (1986)
Osamu Karatsu, Tamio Hoshino, Makoto Endo, Hitoshi Kitazawa, Tohru Adachi, Kazuhiro Ueda
An Integrated Design Automation System for VLSI Circuits. IEEE Des. Test 2 (5) (1985)
Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo
Hierarchical top-down layout design method for VLSI chip. DAC (1982)