Hitoshi Kitazawa

Publication Activity (10 Years)

Years Active: 1982-2017
Publications (10 Years): 6

Top Topics

Moving Object Extraction

Fpga Implementation

Surveillance Cameras

Array Processor

Top Venues

IEICE Trans. Inf. Syst.

Publications

Shota Saito, Yoichi Tomioka, Hitoshi Kitazawa
A Theoretical Framework for Estimating False Acceptance Rate of PRNU-Based Camera Identification. IEEE Trans. Inf. Forensics Secur. 12 (9) (2017)
Ning Li, Shunpei Takaki, Yoichi Tomioka, Hitoshi Kitazawa
A multistage dataflow implementation of a Deep Convolutional Neural Network based on FPGA for high-speed object recognition. SSIAI (2016)
Yutaro Ishigaki, Ning Li, Yoichi Tomioka, Akihiko Miyazaki, Hitoshi Kitazawa
An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only). FPGA (2015)
Ryota Takasu, Yoichi Tomioka, Takashi Aoki, Hitoshi Kitazawa
An FPGA Implementation of Multi-stream Tracking Hardware using 2D SIMD Array (Abstract Only). FPGA (2015)
Yutaro Ishigaki, Yoichi Tomioka, Tsugumichi Shibata, Hitoshi Kitazawa
An FPGA implementation of 3D numerical simulations on a 2D SIMD array processor. ISCAS (2015)
Tetsuya Okuda, Yoichi Tomioka, Hitoshi Kitazawa
Robust Moving Object Extraction and Tracking Method Based on Matching Position Constraints. IEICE Trans. Inf. Syst. (8) (2015)
Ryota Takasu, Yoichi Tomioka, Yutaro Ishigaki, Ning Li, Tsugumichi Shibata, Mamoru Nakanishi, Hitoshi Kitazawa
An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU. IEICE Trans. Electron. (7) (2014)
Sumitaka Ogino, Yoichi Tomioka, Hitoshi Kitazawa
Patrol course planning and battery station placement for mobile surveillance cameras. ICME (2014)
Yoichi Tomioka, Ryota Takasu, Takashi Aoki, Eiichi Hosoya, Hitoshi Kitazawa
FPGA Implementation of Exclusive Block Matching for Robust Moving Object Extraction and Tracking. IEICE Trans. Inf. Syst. (3) (2014)
Yoichi Tomioka, Hikaru Murakami, Hitoshi Kitazawa
Sunshine-Change-Tolerant Moving Object Masking for Realizing both Privacy Protection and Video Surveillance. IEICE Trans. Inf. Syst. (9) (2014)
Yoichi Tomioka, Yuya Ito, Hitoshi Kitazawa
Robust Digital Camera Identification Based on Pairwise Magnitude Relations of Clustered Sensor Pattern Noise. IEEE Trans. Inf. Forensics Secur. 8 (12) (2013)
Zhu Li, Yoichi Tomioka, Hitoshi Kitazawa
Extraction and Tracking Moving Objects in Detail Considering Visual Feature Constraint and Structure Constraint. IEICE Trans. Inf. Syst. (5) (2013)
Yoichi Tomioka, Hitoshi Kitazawa
Collaborative patrol planning of mobile surveillance cameras for perfect observation of moving objects. ICME (2013)
Zhu Li, Kojiro Tomotsune, Yoichi Tomioka, Hitoshi Kitazawa
Template Matching Method Based on Visual Feature Constraint and Structure Constraint. IEICE Trans. Inf. Syst. (8) (2012)
Yoichi Tomioka, Atsushi Takara, Hitoshi Kitazawa
Generation of an Optimum Patrol Course for Mobile Surveillance Camera. IEEE Trans. Circuits Syst. Video Technol. 22 (2) (2012)
Yoichi Tomioka, Hitoshi Kitazawa
Digital camera identification based on the clustered pattern noise of image sensors. ICME (2011)
Yoichi Tomioka, Atsushi Takara, Hitoshi Kitazawa
Enhanced patrol course planning method for multiple mobile surveillance cameras. ICDSC (2011)
Zhu Li, Kenichi Yabuta, Hitoshi Kitazawa
Exclusive Block Matching for Moving Object Extraction and Tracking. IEICE Trans. Inf. Syst. (5) (2010)
Yoichi Tomioka, Atsushi Takara, Hitoshi Kitazawa
Travelling route of mobile surveillance camera. APCCAS (2010)
Zhu Li, Yoichi Tomioka, Hitoshi Kitazawa
Motion estimation based on iterative color matching and structure matching. APCCAS (2010)
Zhu Li, Kenichi Yabuta, Hitoshi Kitazawa
A New Method for Moving Object Extraction and Tracking Based on the Exclusive Block Matching. PSIVT (2009)
Kenichi Yabuta, Hitoshi Kitazawa, Toshihisa Tanaka
Privacy Protection by Masking Moving Objects for Security Cameras. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2009)
Kazuya Matsushita, Hitoshi Kitazawa
An improved camera identification method based on the texture complexity and the image restoration. ICHIT (2009)
Kenichi Yabuta, Hitoshi Kitazawa
Optimum camera placement considering camera specification for security monitoring. ISCAS (2008)
Jun Umezawa, Hitoshi Kitazawa
A vision sensor with background subtraction processor using mixed analog-digital architecture. APCCAS (2008)
Kenichi Yabuta, Hitoshi Kitazawa, Toshihisa Tanaka
A new concept of real-time security camera monitoring with privacy protection by masking moving objects. Real-Time Image Processing (2006)
Hidenori Sato, Hiroto Matsuoka, Hitoshi Kitazawa, Akira Onozawa
Image-Based Photorealistic 3D Reconstruction Using Hexagonal Representation. Inf. Media Technol. 1 (1) (2006)
Kenichi Yabuta, Hitoshi Kitazawa, Toshihisa Tanaka
A New Concept of Security Camera Monitoring with Privacy Protection by Masking Moving Objects. PCM (1) (2005)
Hiroto Matsuoka, Tatsuto Takeuchi, Hitoshi Kitazawa, Akira Onozawa
Representation of Pseudo Inter-reflection and Transparency by Considering Characteristics of Human Vision. Comput. Graph. Forum 21 (3) (2002)
Hidenori Sato, Hiroto Matsuoka, Akira Onozawa, Hitoshi Kitazawa
Hexagonal Image Representation for 3-D Photorealistic Reconstruction. ICPR (2) (2002)
Ikuo Harada, Hidenori Sato, Hitoshi Kitazawa
Optimizing Network 3D Data Transmissions for Interactive Applications. PG (2000)
Y. Takei, Akira Onozawa, K. Kawai, Hitoshi Kitazawa
An Efficient Paired-net Routing Algorithm for High-speed Bipolar LSIs. Great Lakes Symposium on VLSI (1997)
Akira Onozawa, Hitoshi Kitazawa, K. Kawai
Post-layout optimization of power and timing for ECL LSIs. ED&TC (1995)
Ikuo Harada, Hitoshi Kitazawa
A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's. DAC (1994)
Ikuo Harada, Hitoshi Kitazawa, Takao Kaneko
A Routing System for Mixed A/D Standard Cell LSIs. ICCAD (1990)
Kazuhiro Ueda, Hitoshi Kitazawa, Tohru Adachi, Ikuo Harada
Top-Down Layout for Hierarchical Custom Design. IEEE Des. Test 4 (6) (1987)
Takumi Watanabe, Hitoshi Kitazawa, Yoshi Sugiyama
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (2) (1987)
Kazuhiro Ueda, Hitoshi Kitazawa, Ikuo Harada
CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 (1) (1985)
Osamu Karatsu, Tamio Hoshino, Makoto Endo, Hitoshi Kitazawa, Tohru Adachi, Kazuhiro Ueda
An Integrated Design Automation System for VLSI Circuits. IEEE Des. Test 2 (5) (1985)
Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo
Hierarchical top-down layout design method for VLSI chip. DAC (1982)