A multistage dataflow implementation of a Deep Convolutional Neural Network based on FPGA for high-speed object recognition.
Ning LiShunpei TakakiYoichi TomiokaHitoshi KitazawaPublished in: SSIAI (2016)
Keyphrases
- multistage
- high speed
- object recognition
- production system
- stochastic programming
- single stage
- dynamic programming
- hardware implementation
- low power
- neural network
- efficient implementation
- real time
- design methodology
- deep learning
- hardware design
- computer vision
- software implementation
- lot sizing
- multistage stochastic
- fpga device
- hardware architectures
- dedicated hardware
- hardware architecture
- shared memory
- data flow