Tsugumichi Shibata

Publication Activity (10 Years)

Years Active: 1994-2021
Publications (10 Years): 5

Top Topics

Biologically Motivated

Power Management

Fpga Implementation

Top Venues

IEICE Trans. Electron.

IEICE Electron. Express

Publications

Bojun Zheng, Takefumi Masuda, Tsugumichi Shibata
An Indoor Positioning with a Neural Network Model of TensorFlow for Machine Learning. ISPACS (2021)
Tsugumichi Shibata, Yoshito Kato
Characterization of Multi-Layer Ceramic Chip Capacitors up to mm-Wave Frequencies for High-Speed Digital Signal Coupling. IEICE Trans. Electron. (11) (2020)
Chunhui Pan, Hao San, Tsugumichi Shibata
A 720µW 77.93dB SNDR ΔΣ AD Modulator Using Dynamic Analog Components With Simplified Operation Phase. ISPACS (2018)
Chunhui Pan, Hao San, Tsugumichi Shibata
A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode. MIXDES (2017)
Chunhui Pan, Hao San, Tsugumichi Shibata
A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer. ISPACS (2016)
Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. IEICE Trans. Electron. (1) (2015)
Yutaro Ishigaki, Yoichi Tomioka, Tsugumichi Shibata, Hitoshi Kitazawa
An FPGA implementation of 3D numerical simulations on a 2D SIMD array processor. ISCAS (2015)
Ryota Takasu, Yoichi Tomioka, Yutaro Ishigaki, Ning Li, Tsugumichi Shibata, Mamoru Nakanishi, Hitoshi Kitazawa
An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU. IEICE Trans. Electron. (7) (2014)
Tsugumichi Shibata
Foreword. IEICE Trans. Electron. (7) (2014)
Sadayuki Yasuda, Shoko Ohteru, Yasuyuki Itoh, Koji Yamazaki, Yusuke Sekihara, Takashi Aoki, Masami Urano, Tsugumichi Shibata
A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI. IEICE Electron. Express 10 (11) (2013)
Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs. ISCAS (2012)
Shoko Ohteru, Tomoaki Kawamura, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON. A-SSCC (2011)
Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Akihiko Miyazaki, Masami Urano, Tsugumichi Shibata
Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction. GLOBECOM (2011)
Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control. ISOCC (2011)
Hiroaki Katsurai, Hideki Kamitsuna, Hiroshi Koizumi, Jun Terada, Yusuke Ohtomo, Tsugumichi Shibata
An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System. IEICE Trans. Electron. (4) (2011)
Hideyuki Nosaka, Makoto Nakamura, Kimikazu Sano, Minoru Ida, Kenji Kurishima, Tsugumichi Shibata, Masami Tokumitsu, Masahiro Muraguchi
A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation. IEICE Trans. Electron. (6) (2005)
Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. IEEE J. Solid State Circuits 40 (7) (2005)
Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. ESSCIRC (2004)
Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39 (8) (2004)
Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. IEEE J. Solid State Circuits 38 (2) (2003)
Tsugumichi Shibata, Shunji Kimura, Hideaki Kimura, Yuhki Imai, Yohtaro Umeda, Yukio Akazawa
A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module. IEEE J. Solid State Circuits 29 (12) (1994)