A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector.
Hideyuki NosakaEiichi SanoKiyoshi IshiiMinoru IdaKenji KurishimaShoji YamahataTsugumichi ShibataHiroyuki FukuyamaMikio YoneyamaTakatomo EnokiMasahiro MuraguchiPublished in: IEEE J. Solid State Circuits (2004)
Keyphrases
- data sets
- data processing
- data analysis
- original data
- raw data
- data collection
- image data
- database
- machine learning
- statistical methods
- sensor data
- high dimensional data
- input data
- data distribution
- information systems
- high quality
- data structure
- data mining techniques
- high speed
- knowledge discovery
- end users
- prior knowledge
- bayesian networks