Kenji Kurishima

Publication Activity (10 Years)

Years Active: 2002-2019
Publications (10 Years): 3

Top Topics

Top Venues

IEICE Trans. Electron.

IEICE Electron. Express

Publications

Takuya Hoshi, Norihide Kashio, Yuta Shiratori, Kenji Kurishima, Minoru Ida, Hideaki Matsuzaki
and 5.4-V breakdown voltage. IEICE Electron. Express 16 (3) (2019)
Hiroyuki Fukuyama, Michihiro Hirata, Kenji Kurishima, Minoru Ida, Masami Tokumitsu, Shogo Yamanaka, Munehiko Nagatani, Toshihiro Itoh, Kimikazu Sano, Hideyuki Nosaka, Koichi Murata
An InP-Based 27-GHz-Bandwidth Limiting TIA IC Designed to Suppress Undershoot and Ringing in Its Output Waveform. IEICE Trans. Electron. (3) (2016)
Norihide Kashio, Takuya Hoshi, Kenji Kurishima, Minoru Ida, Hideaki Matsuzaki
and 5-V Breakdown Voltage. IEICE Trans. Electron. (5) (2016)
Yves Bouvier, Kimikazu Sano, Munehiko Nagatani, Koichi Murata, Kenji Kurishima, Minoru Ida
-1 PRBS generator. IEICE Electron. Express 9 (19) (2012)
Kenji Kurishima, Minoru Ida, Norihide Kashio, Yoshino K. Fukai
-Type Doped Layer in the Emitter-Base Heterojunction Vicinity. IEICE Trans. Electron. (8) (2012)
Yoshino K. Fukai, Kenji Kurishima, Norihide Kashio, Minoru Ida, Shoji Yamahata, Takatomo Enoki
Emitter-metal-related degradation in InP-based HBTs operating at high current density and its suppression by refractory metal. Microelectron. Reliab. 49 (4) (2009)
Norihide Kashio, Kenji Kurishima, Yoshino K. Fukai, Shoji Yamahata
. IEICE Trans. Electron. (7) (2008)
Hideyuki Nosaka, Makoto Nakamura, Kimikazu Sano, Minoru Ida, Kenji Kurishima, Tsugumichi Shibata, Masami Tokumitsu, Masahiro Muraguchi
A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation. IEICE Trans. Electron. (6) (2005)
Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. IEEE J. Solid State Circuits 40 (7) (2005)
Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. ESSCIRC (2004)
Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39 (8) (2004)
Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors. IEEE J. Solid State Circuits 37 (9) (2002)