Kiyoshi Ishii

Publication Activity (10 Years)

Years Active: 1994-2015
Publications (10 Years): 0

Top Topics

Automatic Analysis

Top Venues

Publications

Yasushi Takahashi, Keisuke Eguchi, Akinobu Itoh, Kiyoshi Ishii
Analysis of propagation-delays in high-speed bipolar gates. ISPACS (2015)
Yuki Hagita, Kiyoshi Ishii
Circuit technique for improving propagation delay times in CMOS source-coupled logic circuits. ISPACS (2012)
Kiyoshi Ishii
Special Section on Functional Thin Films for Optical Applications. IEICE Trans. Electron. (10) (2008)
Kiyoshi Ishii, Yoshifumi Saitou, Kengo Furutani, Hiroshi Sakuma, Yoshito Ikeda
Estimation of Optimum Ion Energy for the Reduction of Resistivity in Bias Sputtering of ITO Thin Films. IEICE Trans. Electron. (10) (2008)
Yongbum Lee, Noriyuki Takahashi, Du-Yih Tsai, Kiyoshi Ishii
Adaptive partial median filter for early CT signs of acute cerebral infarction. Int. J. Comput. Assist. Radiol. Surg. 2 (2) (2007)
Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. IEEE J. Solid State Circuits 40 (7) (2005)
Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. ESSCIRC (2004)
Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39 (8) (2004)
Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. IEEE J. Solid State Circuits 38 (2) (2003)
Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors. IEEE J. Solid State Circuits 37 (9) (2002)
Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino
Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. IEEE J. Solid State Circuits 37 (1) (2002)
Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino
A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. ISCAS (2000)
Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi
Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops. IEEE J. Solid State Circuits 30 (1) (1995)
Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi
Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit. IEEE J. Solid State Circuits 29 (7) (1994)
Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi
High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology. IEEE J. Solid State Circuits 29 (5) (1994)