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Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX.
Keiji Kishine
Kiyoshi Ishii
Haruhiko Ichino
Published in:
IEEE J. Solid State Circuits (2002)
Keyphrases
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parameter optimization
high speed
genetic algorithm ga
differential evolution
genetic algorithm
parameter settings
parameter estimation
support vector machine
pid controller
integrated circuit
real time
genetic programming
fitness function
knn
particle swarm optimization pso
search space
neural network