Haruhiko Ichino

Publication Activity (10 Years)

Years Active: 1994-2007
Publications (10 Years): 0

Publications

Shoko Ohteru, Keiji Kishine, Haruhiko Ichino
MAC protocol based on cross-layer design methodology for fast link in wireless communication systems. IEICE Electron. Express 4 (19) (2007)
Kazuhiko Terada, Kenji Kawai, Osamu Ishida, Keiji Kishine, Noboru Iwasaki, Haruhiko Ichino
Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. IEICE Trans. Commun. (10) (2005)
Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino
PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. IEEE J. Solid State Circuits 39 (5) (2004)
Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino
Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. IEEE J. Solid State Circuits 37 (1) (2002)
Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino
A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. ISCAS (2000)
Kenji Kawai, Haruhiko Ichino
A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI. IEEE J. Solid State Circuits 35 (12) (2000)
Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino
A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs. IEEE J. Solid State Circuits 34 (6) (1999)
Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. IEEE J. Solid State Circuits 34 (1) (1999)
Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. IEEE J. Solid State Circuits 33 (10) (1998)
Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino
A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. IEEE J. Solid State Circuits 32 (2) (1997)
Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi
Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops. IEEE J. Solid State Circuits 30 (1) (1995)
Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi
Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit. IEEE J. Solid State Circuits 29 (7) (1994)
Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi
High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology. IEEE J. Solid State Circuits 29 (5) (1994)