Keiichi Koike

Publication Activity (10 Years)

Years Active: 1998-2010
Publications (10 Years): 0

Publications

Yukikuni Nishida, Kenji Kawai, Keiichi Koike
A 2Gb/s network processor with a 24mW IPsec offload for residential gateways. ISSCC (2010)
Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. IEEE J. Solid State Circuits 34 (1) (1999)
Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. IEEE J. Solid State Circuits 33 (10) (1998)