High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing.
Keiichi KoikeKenji KawaiAkira OnozawaYuichiro TakeiYoshiji KobayashiHaruhiko IchinoPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- low power
- high speed
- design methodology
- signal processing
- digital signal processing
- low cost
- power consumption
- vlsi circuits
- single chip
- physical design
- fuzzy neural network
- image processing
- vlsi architecture
- logic circuits
- power dissipation
- design methodologies
- design process
- low power consumption
- mixed signal
- signal processor
- object oriented
- formal specification
- real time