A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design.
Kenji KawaiKeiichi KoikeYuichiro TakeiAkira OnozawaHitoshi ObaraHaruhiko IchinoPublished in: IEEE J. Solid State Circuits (1999)
Keyphrases
- single chip
- low power
- power consumption
- low cost
- high speed
- low power consumption
- cmos image sensor
- latent semantic indexing
- power dissipation
- cmos technology
- logic circuits
- digital signal processing
- image sensor
- mixed signal
- vlsi architecture
- high power
- wireless transmission
- ultra low power
- power saving
- power reduction
- signal processor
- nm technology
- vlsi circuits
- gate array
- power management
- text retrieval