PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits.
Keiji KishineKyoko FujimotoSatomi KusanagiHaruhiko IchinoPublished in: IEEE J. Solid State Circuits (2004)
Keyphrases
- data analysis
- high speed
- data sets
- data sources
- data collection
- data processing
- data acquisition
- case study
- empirical data
- statistical analysis
- training data
- circuit design
- input data
- image data
- data points
- missing data
- end users
- data mining techniques
- low cost
- design process
- power consumption
- data quality
- correlation analysis
- logic circuits
- delay insensitive
- logic synthesis