Circuit technique for improving propagation delay times in CMOS source-coupled logic circuits.
Yuki HagitaKiyoshi IshiiPublished in: ISPACS (2012)
Keyphrases
- logic circuits
- power dissipation
- low power
- power consumption
- cmos technology
- high speed
- low cost
- functional decomposition
- vlsi circuits
- tunnel diode
- gate array
- chip design
- digital signal processing
- logic synthesis
- nm technology
- finite state machines
- design methodology
- image sensor
- signal processing
- low voltage
- circuit design
- delay insensitive