Hideyuki Nosaka

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 45

Top Topics

Decision Feedback

Top Venues

IEEE J. Solid State Circuits

Publications

Naoki Miura, Hiroaki Taguchi, Kazuyoshi Watanabe, Masaya Nohara, Tatsuyuki Makita, Masahiro Tanabe, Takahiro Wakimoto, Shohei Kumagai, Hideyuki Nosaka, Atsushi Aratake, Toshihiro Okamoto, Shun Watanabe, Jun Takeya, Takeshi Komatsu
17.4 Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes. ISSCC (2024)
Shuichi Inaguma, Koki Nagata, Hideyuki Nosaka
DDS-based Multiphase Local Oscillator Generator for Fast-Beam-Switching Phased-Array Antennas. RWS (2024)
Haruki Shibue, Hideyuki Nosaka
A ROM-Less DDS with Single Current-Switch Array Using Self-Adjusting Two-Step Integrator. RWS (2023)
Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation. IEEE J. Solid State Circuits 57 (8) (2022)
Il-Min Yi, Naoki Miura, Hideyuki Nosaka
A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS. IEEE J. Solid State Circuits 56 (2) (2021)
Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka
A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation. IEEE J. Solid State Circuits 56 (2) (2021)
Ibrahim Abdo, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada
64QAM wireless link with 300GHz InP-CMOS hybrid transceiver. IEICE Electron. Express 18 (17) (2021)
Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada
22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS. ISSCC (2021)
Teruo Jyo, Munehiko Nagatani, Minoru Ida, Miwa Mutoh, Hitoshi Wakita, Naoki Terao, Hideyuki Nosaka
An over 220-GHz-Bandwidth Distributed Active Power Combiner in 250-nm InP DHBT. BCICTS (2020)
Takayuki Kobayashi, Masanori Nakamura, Fukutaro Hamaoka, Munehiko Nagatani, Hiroshi Yamazaki, Hideyuki Nosaka, Yutaka Miyamoto
Long-Haul WDM Transmission with Over-1-Tb/s Channels using Electrically Synthesized High-Symbol-Rate Signals. OFC (2020)
Masanori Nakamura, Takayuki Kobayashi, Hiroshi Yamazaki, Fukutaro Hamaoka, Munehiko Nagatani, Hitoshi Wakita, Hideyuki Nosaka, Yutaka Miyamoto
Entropy and Symbol-Rate Optimized 120 GBaud PS-36QAM Signal Transmission over 2400 km at Net-Rate of 800 Gbps/λ. OFC (2020)
Hiroshi Hamada, Takuya Tsutsumi, Hideaki Matsuzaki, Takuya Fujimura, Ibrahim Abdo, Atsushi Shirane, Kenichi Okada, Go Itami, Ho-Jin Song, Hiroki Sugiyama, Hideyuki Nosaka
300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers. IEEE J. Solid State Circuits 55 (9) (2020)
Hiroshi Hamada, Takuya Tsutsumi, Adam Pander, Masahito Nakamura, Go Itami, Hideaki Matsuzaki, Hiroki Sugiyama, Hideyuki Nosaka
230-305 GHz, > 10-dBm-Output-Power Wideband Power Amplifier Using Low-Q Neutralization Technique in 60-nm InP-HEMT Technology. BCICTS (2020)
Fukutaro Hamaoka, Masahito Nakamura, Munehiko Nagatani, Hitoshi Wakita, Takayuki Kobayashi, Hiroshi Yamazaki, Hideyuki Nosaka, Yutaka Miyamoto
Ultra-wideband Optical Receiver Using Electrical Spectrum Decomposition Technique. ECOC (2020)
Teruo Jyo, Munehiko Nagatani, Josuke Ozaki, Mitsuteru Ishikawa, Hideyuki Nosaka
12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters. ISSCC (2020)
Munehiko Nagatani, Hitoshi Wakita, Hiroshi Yamazaki, Yoshihiro Ogiso, Miwa Mutoh, Minoru Ida, Fukutaro Hamaoka, Masanori Nakamura, Takayuki Kobayashi, Yutaka Miyamoto, Hideyuki Nosaka
A Beyond-1-Tb/s Coherent Optical Transmitter Front-End Based on 110-GHz-Bandwidth 2: 1 Analog Multiplexer in 250-nm InP DHBT. IEEE J. Solid State Circuits 55 (9) (2020)
Toshiki Kishi, Munehiko Nagatani, Shigeru Kanazawa, Kota Shikama, Takuro Fujii, Hidetaka Nishi, Hiroshi Yamazaki, Norio Sato, Hideyuki Nosaka, Shinji Matsuo
A 0.57-mW/Gbps, 2ch × 53-Gbps Low-Power PAM4 Transmitter Front-End Flip-Chip-Bonded 1.3-µm LD-Array-on-Si. OFC (2020)
Nikolaos-Panteleimon Diamantopoulos, Hiroshi Yamazaki, Suguru Yamaoka, Munehiko Nagatani, Hidetaka Nishi, Hiromasa Tanobe, Ryo Nakao, Takuro Fujii, Koji Takeda, Takaaki Kakitsuka, Hitoshi Wakita, Minoru Ida, Hideyuki Nosaka, Fumio Koyama, Yutaka Miyamoto, Shinji Matsuo
Net 321.24-Gb/s IMDD Transmission Based on a >100-GHz Bandwidth Directly-Modulated Laser. OFC (2020)
Takayuki Kobayashi, Shimpei Shimizu, Masahito Nakamura, Takeshi Umeki, Takushi Kazama, Ryoichi Kasahara, Fukutaro Hamaoka, Munehiko Nagatani, Hiroshi Yamazaki, Takayuki Mizuno, Hideyuki Nosaka, Yutaka Miyamoto
Wideband Inline-Amplified WDM Transmission using PPLN-Based OPA with Over-10-THz Bandwidth. OFC (2020)
Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. IEICE Trans. Electron. (10) (2020)
Munehiko Nagatani, Yutaka Miyamoto, Hideyuki Nosaka, Hitoshi Wakita, Yoshihiro Ogiso, Hiroshi Yamazaki, Miwa Mutoh, Minoru Ida, Fukutaro Hamaoka, Masanori Nakamura, Takayuki Kobayashi
A 110-GHz-Bandwidth 2: 1 AMUX-Driver using 250-nm InP DHBTs for Beyond-1-Tb/s/carrier Optical Transmission Systems. BCICTS (2019)
Akira Hida, Yusuke Nakane, Shunta Mizuno, Makoto Nakamura, Daisuke Ito, Shinsuke Nakano, Hideyuki Nosaka
A wideband current-reuse-RGC TIA circuit with low-power consumption. IEICE Electron. Express 16 (22) (2019)
Toshiki Kishi, Hitoshi Wakita, Kota Shikama, Munehiko Nagatani, Shigeru Kanazawa, Takuro Fujii, Hidetaka Nishi, Hiroshi Ishikawa, Yuko Kawajiri, Atsushi Aratake, Hideyuki Nosaka, Hiroshi Fukuda, Shinji Matsuo
A 25-Gbps × 4 ch, Low-Power Compact Wire-Bond-Free 3D-Stacked Transmitter Module with 1.3-μm LD-Array-on-Si for On-Board Optics. OFC (2019)
Fukutaro Hamaoka, Masanori Nakamura, Munehiko Nagatani, Takayuki Kobayashi, Asuka Matsushita, Hitoshi Wakita, Hiroshi Yamazaki, Hideyuki Nosaka, Yutaka Miyamoto
120-GBaud 32QAM Signal Generation using Ultra-Broadband Electrical Bandwidth Doubler. OFC (2019)
Masanori Nakamura, Fukutaro Hamaoka, Munehiko Nagatani, Hiroshi Yamazaki, Takayuki Kobayashi, Asuka Matsushita, Seiji Okamoto, Hitoshi Wakita, Hideyuki Nosaka, Yutaka Miyamoto
1.04 Tbps/Carrier Probabilistically Shaped PDM-64QAM WDM Transmission Over 240 km Based on Electrical Spectrum Synthesis. OFC (2019)
Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. SoCC (2019)
Takayuki Kobayashi, Masanori Nakamura, Fukutaro Hamaoka, Munehiko Nagatani, Hitoshi Wakita, Hiroshi Yamazaki, Takeshi Umeki, Hideyuki Nosaka, Yutaka Miyamoto
35-Tb/s C-Band Transmission Over 800 km Employing 1-Tb/s PS-64QAM Signals Enhanced by Complex 8 × 2 MIMO Equalizer. OFC (2019)
Hiroshi Yamazaki, Munehiko Nagatani, Hitoshi Wakita, Masanori Nakamura, Fukutaro Hamaoka, Takayuki Kobayashi, Yoshihiro Ogiso, Minoru Ida, Toshikazu Hashimoto, Hideyuki Nosaka, Yutaka Miyamoto
Digital-Preprocessed Analog-Multiplexed DAC for High-Speed Optical Communications. OECC/PSC (2019)
Hiroshi Hamada, Takuya Tsutsumi, Go Itami, Hiroki Sugiyama, Hideaki Matsuzaki, Kenichi Okada, Hideyuki Nosaka
300-GHz 120-Gb/s Wireless Transceiver with High-Output-Power and High-Gain Power Amplifier Based on 80-nm InP-HEMT Technology. BCICTS (2019)
Masanori Nakamura, Fukutaro Hamaoka, Munehiko Nagatani, Yoshihiro Ogiso, Hitoshi Wakita, Hiroshi Yamazaki, Takayuki Kobayashi, Minoru Ida, Hideyuki Nosaka, Yutaka Miyamoto
192-Gbaud Signal Generation using Ultra-Broadband Optical Frontend Module Integrated with Bandwidth Multiplexing Function. OFC (2019)
Toshiki Kishi, Munehiko Nagatani, Shigeru Kanazawa, Shinsuke Nakano, Hiroaki Katsurai, Takuro Fujii, Hidetaka Nishi, Takaaki Kakitsuka, Koichi Hasebe, Kota Shikama, Yuko Kawajiri, Atsushi Aratake, Hideyuki Nosaka, Hiroshi Fukuda, Shinji Matsuo
A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si. OFC (2018)
Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka
A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation. A-SSCC (2018)
Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. A-SSCC (2018)
Hiroshi Yamazaki, Munehiko Nagatani, Hitoshi Wakita, Yoshihiro Ogiso, Masanori Nakamura, Minoru Ida, Toshikazu Hashimoto, Hideyuki Nosaka, Yutaka Miyamoto
Transmission of 400-Gbps Discrete Multi-Tone Signal Using >100-GHz-Bandwidth Analog Multiplexer and InP Mach-Zehnder Modulator. ECOC (2018)
Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka
MOS D-flip-flop in 65-nm CMOS. VLSI-DAT (2018)
Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka
A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2018)
Munehiko Nagatani, Hitoshi Wakita, Teruo Jyo, Miwa Mutoh, Minoru Ida, Sorin P. Voinigescu, Hideyuki Nosaka
A 256-Gbps PAM-4 Signal Generator IC in 0.25-µm InP DHBT Technology. BCICTS (2018)
Shinsuke Nakano, Munehiko Nagatani, Kenji Tanaka, Yoshihiro Ogiso, Josuke Ozaki, Hiroshi Yamazaki, Hideyuki Nosaka
A 180-mW Linear MZM Driver in CMOS for Single-Carrier 400-Gb/s Coherent Optical Transmitter. ECOC (2017)
Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. ISCAS (2017)
Hiroshi Yamazaki, Munehiko Nagatani, Fukutaro Hamaoka, Shigeru Kanazawa, Hideyuki Nosaka, Toshikazu Hashimoto, Yutaka Miyamoto
Ultra-Wideband Digital-to-Analog Conversion Technologies for Tbit/s channel transmission. ECOC (2017)
Yohan Frans, Ichiro Fujimori, Seung-Jun Bae, Samuel Palermo, Hideyuki Nosaka, Simone Erba
F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. ISSCC (2017)
Samuel Palermo, Hideyuki Nosaka, Frank O'Mahony
Session 29 overview: Optical- and electrical-link innovations. ISSCC (2017)
Munehiko Nagatani, Hideyuki Nosaka
High-performance compound-semiconductor integrated circuits for advanced digital coherent optical communications systems. IEICE Electron. Express 13 (18) (2016)
Hiroyuki Fukuyama, Michihiro Hirata, Kenji Kurishima, Minoru Ida, Masami Tokumitsu, Shogo Yamanaka, Munehiko Nagatani, Toshihiro Itoh, Kimikazu Sano, Hideyuki Nosaka, Koichi Murata
An InP-Based 27-GHz-Bandwidth Limiting TIA IC Designed to Suppress Undershoot and Ringing in Its Output Waveform. IEICE Trans. Electron. (3) (2016)
Ichiro Fujimori, Martin Brox, Elad Alon, Pavan Kumar Hanumolu, Gerrit den Besten, Hideyuki Nosaka
F4: Emerging short-reach and high-density interconnect solutions for internet of everything. ISSCC (2016)
Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. A-SSCC (2015)
Hiroshi Yamazaki, Munehiko Nagatani, Shigeru Kanazawa, Hideyuki Nosaka, Toshikazu Hashimoto, Akihide Sano, Yutaka Miyamoto
160-Gbps Nyquist PAM4 transmitter using a digital-preprocessed analog-multiplexed DAC. ECOC (2015)
Hitoshi Wakita, Munehiko Nagatani, Shigeru Kanazawa, Toshihiro Itoh, Eiichi Yamada, Hiroyuki Ishii, Hideyuki Nosaka
28 Gbaud 16-QAM modulation with compact driver module for InP MZM. IEICE Electron. Express 12 (20) (2015)
Akihide Sano, Munehiko Nagatani, Hideyuki Nosaka, Yutaka Miyamoto
5 × 1-Tb/s PDM-16QAM transmission over 1, 920 km using high-speed InP MUX-DAC integrated module. OFC (2015)
Kimikazu Sano, Hiroyuki Fukuyama, Makoto Nakamura, Miwa Mutoh, Hideyuki Nosaka, Koichi Murata
Wide dynamic range transimpedance amplifier IC for 100-G DP-QPSK optical links using 1-µm InP HBTs. IEICE Electron. Express 9 (12) (2012)
Munehiko Nagatani, Hideyuki Nosaka, Shogo Yamanaka, Kimikazu Sano, Koichi Murata
Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems. IEEE J. Solid State Circuits 46 (10) (2011)
Munehiko Nagatani, Hideyuki Nosaka, Shogo Yamanaka, Kimikazu Sano, Koichi Murata
A 24-GS/s 6-bit R-2R Current-Steering DAC in InP HBT Technology. IEICE Trans. Electron. (8) (2010)
Hideyuki Nosaka, Makoto Nakamura, Kimikazu Sano, Minoru Ida, Kenji Kurishima, Tsugumichi Shibata, Masami Tokumitsu, Masahiro Muraguchi
A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation. IEICE Trans. Electron. (6) (2005)
Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. IEEE J. Solid State Circuits 40 (7) (2005)
Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. ESSCIRC (2004)
Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39 (8) (2004)
Hideyuki Nosaka, Yo Yamaguchi, Akihiro Yamagishi, Masahiro Muraguchi
A Fractional Phase Interpolator Using Two-Step Integration for Frequency Multiplication and Direct Digital Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2003)
Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. IEEE J. Solid State Circuits 38 (2) (2003)
Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors. IEEE J. Solid State Circuits 37 (9) (2002)
Hideyuki Nosaka, Yo Yamaguchi, Akihiro Yamagishi, Hiroyuki Fukuyama, Masahiro Muraguchi
A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique. IEEE J. Solid State Circuits 36 (8) (2001)
Tadao Nakagawa, Hideyuki Nosaka
Authors' Reply. IEEE J. Solid State Circuits 33 (1) (1998)
Tadao Nakagawa, Hideyuki Nosaka
A direct digital synthesizer with interpolation circuits. IEEE J. Solid State Circuits 32 (5) (1997)